/[gxemul]/trunk/src/cpus/memory_sh.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/memory_sh.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8295 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: memory_sh.c,v 1.15 2007/01/29 18:06:37 debug Exp $
29 */
30
31 #include <stdio.h>
32 #include <stdlib.h>
33 #include <string.h>
34
35 #include "cpu.h"
36 #include "machine.h"
37 #include "memory.h"
38 #include "misc.h"
39
40 #include "sh4_exception.h"
41 #include "sh4_mmu.h"
42
43
44 /*
45 * translate_via_mmu():
46 *
47 * Scan the UTLB for a matching virtual address. If a match was found, then
48 * check permission bits etc. If everything was ok, then return the physical
49 * page address, otherwise cause an exception.
50 *
51 * The implementation should (hopefully) be quite complete, except for lack
52 * of "Multiple matching entries" detection. (On a real CPU, these would
53 * cause exceptions.)
54 *
55 * Same return values as sh_translate_v2p().
56 */
57 static int translate_via_mmu(struct cpu *cpu, uint32_t vaddr,
58 uint64_t *return_paddr, int flags)
59 {
60 int wf = flags & FLAG_WRITEFLAG;
61 int i, urb, urc, require_asid_match, cur_asid, expevt = 0;
62 uint32_t hi, lo = 0, mask = 0;
63 int sh; /* Shared */
64 int d; /* Dirty bit */
65 int v; /* Valid bit */
66 int pr; /* Protection */
67 int i_start;
68
69 cur_asid = cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK;
70 require_asid_match = !(cpu->cd.sh.mmucr & SH4_MMUCR_SV)
71 || !(cpu->cd.sh.sr & SH_SR_MD);
72
73 if (!(flags & FLAG_NOEXCEPTIONS)) {
74 /*
75 * Increase URC every time the UTLB is accessed. (Note:
76 * According to the SH4 manual, the URC should not be
77 * increased when running the ldtlb instruction. Perhaps this
78 * is a good place? Perhaps it is better to just set it to a
79 * random value? TODO: Find out.
80 */
81 urb = (cpu->cd.sh.mmucr & SH4_MMUCR_URB_MASK) >>
82 SH4_MMUCR_URB_SHIFT;
83 urc = (cpu->cd.sh.mmucr & SH4_MMUCR_URC_MASK) >>
84 SH4_MMUCR_URC_SHIFT;
85
86 /* fatal("urc = %i ==> ", urc); */
87 urc ++;
88 if (urc == SH_N_UTLB_ENTRIES || (urb > 0 && urc == urb))
89 urc = 0;
90 /* fatal("%i\n", urc); */
91
92 cpu->cd.sh.mmucr &= ~SH4_MMUCR_URC_MASK;
93 cpu->cd.sh.mmucr |= (urc << SH4_MMUCR_URC_SHIFT);
94 }
95
96 /*
97 * When doing Instruction lookups, the ITLB should be scanned first.
98 * This is done by using negative i. (Ugly hack, but works.)
99 */
100 if (flags & FLAG_INSTR)
101 i_start = -SH_N_ITLB_ENTRIES;
102 else
103 i_start = 0;
104
105 for (i=i_start; i<SH_N_UTLB_ENTRIES; i++) {
106 if (i<0) {
107 hi = cpu->cd.sh.itlb_hi[i + SH_N_ITLB_ENTRIES];
108 lo = cpu->cd.sh.itlb_lo[i + SH_N_ITLB_ENTRIES];
109 } else {
110 hi = cpu->cd.sh.utlb_hi[i];
111 lo = cpu->cd.sh.utlb_lo[i];
112 }
113 mask = 0xfff00000;
114
115 v = lo & SH4_PTEL_V;
116
117 switch (lo & SH4_PTEL_SZ_MASK) {
118 case SH4_PTEL_SZ_1K: mask = 0xfffffc00; break;
119 case SH4_PTEL_SZ_4K: mask = 0xfffff000; break;
120 case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
121 /* case SH4_PTEL_SZ_1M: mask = 0xfff00000; break; */
122 }
123
124 if (!v || (hi & mask) != (vaddr & mask))
125 continue;
126
127 sh = lo & SH4_PTEL_SH;
128
129 if (!sh && require_asid_match) {
130 int asid = hi & SH4_PTEH_ASID_MASK;
131 if (asid != cur_asid)
132 continue;
133 }
134
135 /* Note/TODO: Check for multiple matches is not implemented. */
136
137 break;
138 }
139
140 /* Virtual address not found? Then it's a TLB miss. */
141 if (i == SH_N_UTLB_ENTRIES)
142 goto tlb_miss;
143
144 /* Matching address found! Let's see it is readable/writable, etc: */
145 d = lo & SH4_PTEL_D;
146 pr = (lo & SH4_PTEL_PR_MASK) >> SH4_PTEL_PR_SHIFT;
147
148 *return_paddr = (vaddr & ~mask) | (lo & mask & 0x1fffffff);
149
150 if (flags & FLAG_INSTR) {
151 /*
152 * Instruction access:
153 *
154 * If a matching entry wasn't found in the ITLB, but in the
155 * UTLB, then copy it to a random place in the ITLB.
156 */
157 if (i >= 0) {
158 int r = random() % SH_N_ITLB_ENTRIES;
159
160 /* NOTE: Make sure that the old mapping for
161 that itlb entry is invalidated: */
162 cpu->invalidate_translation_caches(cpu,
163 cpu->cd.sh.itlb_hi[r] & ~0xfff, INVALIDATE_VADDR);
164
165 cpu->invalidate_code_translation(cpu,
166 cpu->cd.sh.utlb_lo[i] & ~0xfff, INVALIDATE_PADDR);
167
168 cpu->cd.sh.itlb_hi[r] = cpu->cd.sh.utlb_hi[i];
169 cpu->cd.sh.itlb_lo[r] = cpu->cd.sh.utlb_lo[i];
170 }
171
172 /* Permission checks: */
173 if (cpu->cd.sh.sr & SH_SR_MD)
174 return 1;
175 if (!(pr & 2))
176 goto protection_violation;
177
178 return 1;
179 }
180
181 /* Data access: */
182 if (cpu->cd.sh.sr & SH_SR_MD) {
183 /* Kernel access: */
184 switch (pr) {
185 case 0:
186 case 2: if (wf)
187 goto protection_violation;
188 return 1;
189 case 1:
190 case 3: if (wf && !d)
191 goto initial_write_exception;
192 return 1;
193 }
194 }
195
196 /* User access */
197 switch (pr) {
198 case 0:
199 case 1: goto protection_violation;
200 case 2: if (wf)
201 goto protection_violation;
202 return 1;
203 case 3: if (wf && !d)
204 goto initial_write_exception;
205 return 1;
206 }
207
208
209 tlb_miss:
210 expevt = wf? EXPEVT_TLB_MISS_ST : EXPEVT_TLB_MISS_LD;
211 goto exception;
212
213 protection_violation:
214 expevt = wf? EXPEVT_TLB_PROT_ST : EXPEVT_TLB_PROT_LD;
215 goto exception;
216
217 initial_write_exception:
218 expevt = EXPEVT_TLB_MOD;
219
220
221 exception:
222 if (flags & FLAG_NOEXCEPTIONS) {
223 *return_paddr = 0;
224 return 2;
225 }
226
227 sh_exception(cpu, expevt, 0, vaddr);
228
229 return 0;
230 }
231
232
233 /*
234 * sh_translate_v2p():
235 *
236 * Return values:
237 *
238 * 0 No access to the virtual address.
239 * 1 return_paddr contains the physical address, the page is
240 * available as read-only.
241 * 2 Same as 1, but the page is available as read/write.
242 */
243 int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_paddr,
244 int flags)
245 {
246 int user = cpu->cd.sh.sr & SH_SR_MD? 0 : 1;
247
248 vaddr = (uint32_t)vaddr;
249
250 /* U0/P0: Userspace addresses, or P3: Kernel virtual memory. */
251 if (!(vaddr & 0x80000000) ||
252 (vaddr >= 0xc0000000 && vaddr < 0xe0000000)) {
253 /* Address translation turned off? */
254 if (!(cpu->cd.sh.mmucr & SH4_MMUCR_AT)) {
255 /* Then return raw physical address: */
256 *return_paddr = vaddr & 0x1fffffff;
257 return 2;
258 }
259
260 /* Perform translation via the MMU: */
261 return translate_via_mmu(cpu, vaddr, return_paddr, flags);
262 }
263
264 /* Store queue region: */
265 if (vaddr >= 0xe0000000 && vaddr < 0xe4000000) {
266 /* Note/TODO: Take SH4_MMUCR_SQMD into account. */
267 *return_paddr = vaddr;
268 return 2;
269 }
270
271 if (user) {
272 if (flags & FLAG_NOEXCEPTIONS) {
273 *return_paddr = 0;
274 return 2;
275 }
276
277 fatal("Userspace tried to access non-user space memory."
278 " TODO: cause exception! (vaddr=0x%08"PRIx32"\n",
279 (uint32_t) vaddr);
280 exit(1);
281 }
282
283 /* P1,P2: Direct-mapped physical memory. */
284 if (vaddr >= 0x80000000 && vaddr < 0xc0000000) {
285 *return_paddr = vaddr & 0x1fffffff;
286 return 2;
287 }
288
289 if (flags & FLAG_INSTR) {
290 fatal("TODO: instr at 0x%08"PRIx32"\n", (uint32_t)vaddr);
291 exit(1);
292 }
293
294 /* P4: Special registers mapped at 0xf0000000 .. 0xffffffff: */
295 if ((vaddr & 0xf0000000) == 0xf0000000) {
296 *return_paddr = vaddr;
297 return 2;
298 }
299
300 if (flags & FLAG_NOEXCEPTIONS) {
301 *return_paddr = 0;
302 return 2;
303 }
304
305 /* TODO */
306 fatal("Unimplemented SH vaddr 0x%08"PRIx32"\n", (uint32_t)vaddr);
307 exit(1);
308 }
309
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