/[gxemul]/trunk/src/cpus/memory_sh.c
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Contents of /trunk/src/cpus/memory_sh.c

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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 8598 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 /*
2 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: memory_sh.c,v 1.23 2007/06/05 06:41:30 debug Exp $
29 */
30
31 #include <stdio.h>
32 #include <stdlib.h>
33 #include <string.h>
34
35 #include "cpu.h"
36 #include "machine.h"
37 #include "memory.h"
38 #include "misc.h"
39
40 #include "sh4_exception.h"
41 #include "sh4_mmu.h"
42
43
44 /*
45 * translate_via_mmu():
46 *
47 * Scan the UTLB for a matching virtual address. If a match was found, then
48 * check permission bits etc. If everything was ok, then return the physical
49 * page address, otherwise cause an exception.
50 *
51 * The implementation should (hopefully) be quite complete, except for lack
52 * of "Multiple matching entries" detection. (On a real CPU, these would
53 * cause exceptions.)
54 *
55 * Same return values as sh_translate_v2p().
56 */
57 static int translate_via_mmu(struct cpu *cpu, uint32_t vaddr,
58 uint64_t *return_paddr, int flags)
59 {
60 int wf = flags & FLAG_WRITEFLAG;
61 int i, urb, urc, require_asid_match, cur_asid, expevt = 0;
62 uint32_t hi, lo = 0, mask = 0;
63 int sh; /* Shared */
64 int d; /* Dirty bit */
65 int v; /* Valid bit */
66 int pr; /* Protection */
67 int i_start;
68
69 cur_asid = cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK;
70 require_asid_match = !(cpu->cd.sh.mmucr & SH4_MMUCR_SV)
71 || !(cpu->cd.sh.sr & SH_SR_MD);
72
73 if (!(flags & FLAG_NOEXCEPTIONS)) {
74 /*
75 * Increase URC every time the UTLB is accessed. (Note:
76 * According to the SH4 manual, the URC should not be
77 * increased when running the ldtlb instruction. Perhaps this
78 * is a good place? Perhaps it is better to just set it to a
79 * random value? TODO: Find out.
80 */
81 urb = (cpu->cd.sh.mmucr & SH4_MMUCR_URB_MASK) >>
82 SH4_MMUCR_URB_SHIFT;
83 urc = (cpu->cd.sh.mmucr & SH4_MMUCR_URC_MASK) >>
84 SH4_MMUCR_URC_SHIFT;
85
86 /* fatal("urc = %i ==> ", urc); */
87 urc ++;
88 if (urc >= SH_N_UTLB_ENTRIES || (urb > 0 && urc == urb))
89 urc = 0;
90 /* fatal("%i\n", urc); */
91
92 cpu->cd.sh.mmucr &= ~SH4_MMUCR_URC_MASK;
93 cpu->cd.sh.mmucr |= (urc << SH4_MMUCR_URC_SHIFT);
94 }
95
96 /*
97 * When doing Instruction lookups, the ITLB should be scanned first.
98 * This is done by using negative i. (Ugly hack, but works.)
99 */
100 if (flags & FLAG_INSTR)
101 i_start = -SH_N_ITLB_ENTRIES;
102 else
103 i_start = 0;
104
105 for (i=i_start; i<SH_N_UTLB_ENTRIES; i++) {
106 if (i<0) {
107 hi = cpu->cd.sh.itlb_hi[i + SH_N_ITLB_ENTRIES];
108 lo = cpu->cd.sh.itlb_lo[i + SH_N_ITLB_ENTRIES];
109 } else {
110 hi = cpu->cd.sh.utlb_hi[i];
111 lo = cpu->cd.sh.utlb_lo[i];
112 }
113 mask = 0xfff00000;
114
115 v = lo & SH4_PTEL_V;
116 if (!v)
117 continue;
118
119 switch (lo & SH4_PTEL_SZ_MASK) {
120 case SH4_PTEL_SZ_1K: mask = 0xfffffc00; break;
121 case SH4_PTEL_SZ_4K: mask = 0xfffff000; break;
122 case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
123 /* case SH4_PTEL_SZ_1M: mask = 0xfff00000; break; */
124 }
125
126 if ((hi & mask) != (vaddr & mask))
127 continue;
128
129 sh = lo & SH4_PTEL_SH;
130
131 if (!sh && require_asid_match) {
132 int asid = hi & SH4_PTEH_ASID_MASK;
133 if (asid != cur_asid)
134 continue;
135 }
136
137 /* Note/TODO: Check for multiple matches is not implemented. */
138
139 break;
140 }
141
142 /* Virtual address not found? Then it's a TLB miss. */
143 if (i == SH_N_UTLB_ENTRIES)
144 goto tlb_miss;
145
146 /* Matching address found! Let's see whether it is
147 readable/writable, etc.: */
148 d = lo & SH4_PTEL_D? 1 : 0;
149 pr = (lo & SH4_PTEL_PR_MASK) >> SH4_PTEL_PR_SHIFT;
150
151 *return_paddr = (vaddr & ~mask) | (lo & mask & 0x1fffffff);
152
153 if (flags & FLAG_INSTR) {
154 /*
155 * Instruction access:
156 */
157 #if 0
158 /* NOTE: Emulating the ITLB as exact as this is not
159 necessary... so I'm disabling it for now. */
160 /*
161 * If a matching entry wasn't found in the ITLB, but in the
162 * UTLB, then copy it to a random place in the ITLB.
163 */
164 if (i >= 0 && !(flags & FLAG_NOEXCEPTIONS)) {
165 int r = random() % SH_N_ITLB_ENTRIES;
166
167 /* NOTE: Make sure that the old mapping for
168 that itlb entry is invalidated: */
169 cpu->invalidate_translation_caches(cpu,
170 cpu->cd.sh.itlb_hi[r] & ~0xfff, INVALIDATE_VADDR);
171
172 cpu->invalidate_code_translation(cpu,
173 cpu->cd.sh.utlb_lo[i] & ~0xfff, INVALIDATE_PADDR);
174
175 cpu->cd.sh.itlb_hi[r] = cpu->cd.sh.utlb_hi[i];
176 cpu->cd.sh.itlb_lo[r] = cpu->cd.sh.utlb_lo[i];
177 }
178 #endif
179
180 /* Permission checks: */
181 if (cpu->cd.sh.sr & SH_SR_MD)
182 return 1;
183 if (!(pr & 2))
184 goto protection_violation;
185
186 return 1;
187 }
188
189 /* Data access: */
190 if (cpu->cd.sh.sr & SH_SR_MD) {
191 /* Kernel access: */
192 switch (pr) {
193 case 0:
194 case 2: if (wf)
195 goto protection_violation;
196 return 1;
197 case 1:
198 case 3: if (wf && !d)
199 goto initial_write_exception;
200 return 1 + d;
201 }
202 }
203
204 /* User access */
205 switch (pr) {
206 case 0:
207 case 1: goto protection_violation;
208 case 2: if (wf)
209 goto protection_violation;
210 return 1;
211 case 3: if (wf && !d)
212 goto initial_write_exception;
213 return 1 + d;
214 }
215
216
217 tlb_miss:
218 expevt = wf? EXPEVT_TLB_MISS_ST : EXPEVT_TLB_MISS_LD;
219 goto exception;
220
221 protection_violation:
222 expevt = wf? EXPEVT_TLB_PROT_ST : EXPEVT_TLB_PROT_LD;
223 goto exception;
224
225 initial_write_exception:
226 expevt = EXPEVT_TLB_MOD;
227
228
229 exception:
230 if (flags & FLAG_NOEXCEPTIONS) {
231 *return_paddr = 0;
232 return 2;
233 }
234
235 sh_exception(cpu, expevt, 0, vaddr);
236
237 return 0;
238 }
239
240
241 /*
242 * sh_translate_v2p():
243 *
244 * Return values:
245 *
246 * 0 No access to the virtual address.
247 * 1 return_paddr contains the physical address, the page is
248 * available as read-only.
249 * 2 Same as 1, but the page is available as read/write.
250 */
251 int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr,
252 int flags)
253 {
254 int user = cpu->cd.sh.sr & SH_SR_MD? 0 : 1;
255 uint32_t vaddr = vaddr64;
256
257 /* U0/P0: Userspace addresses, or P3: Kernel virtual memory. */
258 if (!(vaddr & 0x80000000) ||
259 (vaddr >= 0xc0000000 && vaddr < 0xe0000000)) {
260 /* Address translation turned off? */
261 if (!(cpu->cd.sh.mmucr & SH4_MMUCR_AT)) {
262 /* Then return raw physical address: */
263 *return_paddr = vaddr & 0x1fffffff;
264 return 2;
265 }
266
267 /* Perform translation via the MMU: */
268 return translate_via_mmu(cpu, vaddr, return_paddr, flags);
269 }
270
271 /* Store queue region: */
272 if (vaddr >= 0xe0000000 && vaddr < 0xe4000000) {
273 /* Note/TODO: Take SH4_MMUCR_SQMD into account. */
274 *return_paddr = vaddr;
275 return 2;
276 }
277
278 if (user) {
279 if (flags & FLAG_NOEXCEPTIONS) {
280 *return_paddr = 0;
281 return 2;
282 }
283
284 fatal("Userspace tried to access non-user space memory."
285 " TODO: cause exception! (vaddr=0x%08"PRIx32"\n",
286 (uint32_t) vaddr);
287 exit(1);
288 }
289
290 /* P1,P2: Direct-mapped physical memory. */
291 if (vaddr >= 0x80000000 && vaddr < 0xc0000000) {
292 *return_paddr = vaddr & 0x1fffffff;
293 return 2;
294 }
295
296 if (flags & FLAG_INSTR) {
297 fatal("TODO: instr at 0x%08"PRIx32"\n", (uint32_t)vaddr);
298 exit(1);
299 }
300
301 /* P4: Special registers mapped at 0xf0000000 .. 0xffffffff: */
302 if ((vaddr & 0xf0000000) == 0xf0000000) {
303 *return_paddr = vaddr;
304 return 2;
305 }
306
307 if (flags & FLAG_NOEXCEPTIONS) {
308 *return_paddr = 0;
309 return 2;
310 }
311
312 /* TODO */
313
314 /* The ugly 'if' is just here to fool Compaq CC. */
315 if (!(flags & FLAG_NOEXCEPTIONS)) {
316 fatal("Unimplemented SH vaddr 0x%08"PRIx32"\n", vaddr);
317 exit(1);
318 }
319
320 return 0;
321 }
322

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