/[gxemul]/trunk/src/cpus/memory_sh.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/memory_sh.c

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Revision 32 - (hide annotations)
Mon Oct 8 16:20:58 2007 UTC (13 years, 3 months ago) by dpavlin
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File size: 7996 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 dpavlin 30 /*
2     * Copyright (C) 2006 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 32 * $Id: memory_sh.c,v 1.12 2006/10/28 04:00:32 debug Exp $
29 dpavlin 30 */
30    
31     #include <stdio.h>
32     #include <stdlib.h>
33     #include <string.h>
34    
35     #include "cpu.h"
36     #include "machine.h"
37     #include "memory.h"
38     #include "misc.h"
39    
40 dpavlin 32 #include "sh4_exception.h"
41     #include "sh4_mmu.h"
42 dpavlin 30
43 dpavlin 32
44 dpavlin 30 /*
45 dpavlin 32 * translate_via_mmu():
46     *
47     * Scan the UTLB for a matching virtual address. If a match was found, then
48     * check permission bits etc. If everything was ok, then return the physical
49     * page address, otherwise cause an exception.
50     *
51     * The implementation should (hopefully) be quite complete, except for lack
52     * of "Multiple matching entries" detection. (On a real CPU, these would
53     * cause exceptions.)
54     *
55     * Same return values as sh_translate_v2p().
56 dpavlin 30 */
57 dpavlin 32 static int translate_via_mmu(struct cpu *cpu, uint32_t vaddr,
58 dpavlin 30 uint64_t *return_paddr, int flags)
59     {
60 dpavlin 32 int wf = flags & FLAG_WRITEFLAG;
61     int i, urb, urc, require_asid_match, cur_asid, expevt = 0;
62     uint32_t hi, lo = 0, mask = 0;
63     int sh; /* Shared */
64     int d; /* Dirty bit */
65     int v; /* Valid bit */
66     int pr; /* Protection */
67     int i_start;
68 dpavlin 30
69 dpavlin 32 cur_asid = cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK;
70     require_asid_match = !(cpu->cd.sh.mmucr & SH4_MMUCR_SV)
71     || !(cpu->cd.sh.sr & SH_SR_MD);
72    
73     if (!(flags & FLAG_NOEXCEPTIONS)) {
74     /*
75     * Increase URC every time the UTLB is accessed. (Note:
76     * According to the SH4 manual, the URC should not be
77     * increased when running the ldtlb instruction. Perhaps this
78     * is a good place? Perhaps it is better to just set it to a
79     * random value? TODO: Find out.
80     */
81     urb = (cpu->cd.sh.mmucr & SH4_MMUCR_URB_MASK) >>
82     SH4_MMUCR_URB_SHIFT;
83     urc = (cpu->cd.sh.mmucr & SH4_MMUCR_URC_MASK) >>
84     SH4_MMUCR_URC_SHIFT;
85    
86     /* fatal("urc = %i ==> ", urc); */
87     urc ++;
88     if (urc == SH_N_UTLB_ENTRIES || (urb > 0 && urc == urb))
89     urc = 0;
90     /* fatal("%i\n", urc); */
91    
92     cpu->cd.sh.mmucr &= ~SH4_MMUCR_URC_MASK;
93     cpu->cd.sh.mmucr |= (urc << SH4_MMUCR_URC_SHIFT);
94     }
95    
96     /*
97     * When doing Instruction lookups, the ITLB should be scanned first.
98     * This is done by using negative i. (Ugly hack, but works.)
99     */
100     if (flags & FLAG_INSTR)
101     i_start = -SH_N_ITLB_ENTRIES;
102     else
103     i_start = 0;
104    
105     for (i=i_start; i<SH_N_UTLB_ENTRIES; i++) {
106     if (i<0) {
107     hi = cpu->cd.sh.itlb_hi[i + SH_N_ITLB_ENTRIES];
108     lo = cpu->cd.sh.itlb_lo[i + SH_N_ITLB_ENTRIES];
109     } else {
110     hi = cpu->cd.sh.utlb_hi[i];
111     lo = cpu->cd.sh.utlb_lo[i];
112     }
113     mask = 0xfff00000;
114    
115     v = lo & SH4_PTEL_V;
116    
117     switch (lo & SH4_PTEL_SZ_MASK) {
118     case SH4_PTEL_SZ_1K: mask = 0xfffffc00; break;
119     case SH4_PTEL_SZ_4K: mask = 0xfffff000; break;
120     case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
121     /* case SH4_PTEL_SZ_1M: mask = 0xfff00000; break; */
122     }
123    
124     if (!v || (hi & mask) != (vaddr & mask))
125     continue;
126    
127     sh = lo & SH4_PTEL_SH;
128    
129     if (!sh && require_asid_match) {
130     int asid = hi & SH4_PTEH_ASID_MASK;
131     if (asid != cur_asid)
132     continue;
133     }
134    
135     /* Note/TODO: Check for multiple matches is not implemented. */
136    
137     break;
138     }
139    
140     /* Virtual address not found? Then it's a TLB miss. */
141     if (i == SH_N_UTLB_ENTRIES)
142     goto tlb_miss;
143    
144     /* Matching address found! Let's see it is readable/writable, etc: */
145     d = lo & SH4_PTEL_D;
146     pr = (lo & SH4_PTEL_PR_MASK) >> SH4_PTEL_PR_SHIFT;
147    
148     *return_paddr = (vaddr & ~mask) | (lo & mask & 0x1fffffff);
149    
150     if (flags & FLAG_INSTR) {
151     /*
152     * Instruction access:
153     *
154     * If a matching entry wasn't found in the ITLB, but in the
155     * UTLB, then copy it to a random place in the ITLB.
156     */
157     if (i >= 0) {
158     int r = random() % SH_N_ITLB_ENTRIES;
159     cpu->cd.sh.itlb_hi[r] = cpu->cd.sh.utlb_hi[i];
160     cpu->cd.sh.itlb_lo[r] = cpu->cd.sh.utlb_lo[i];
161     }
162    
163     /* Permission checks: */
164     if (cpu->cd.sh.sr & SH_SR_MD)
165     return 1;
166     if (!(pr & 2))
167     goto protection_violation;
168    
169     return 1;
170     }
171    
172     /* Data access: */
173     if (cpu->cd.sh.sr & SH_SR_MD) {
174     /* Kernel access: */
175     switch (pr) {
176     case 0:
177     case 2: if (wf)
178     goto protection_violation;
179     return 1;
180     case 1:
181     case 3: if (wf && !d)
182     goto initial_write_exception;
183     return 1;
184     }
185     }
186    
187     /* User access */
188     switch (pr) {
189     case 0:
190     case 1: goto protection_violation;
191     case 2: if (wf)
192     goto protection_violation;
193     return 1;
194     case 3: if (wf && !d)
195     goto initial_write_exception;
196     return 1;
197     }
198    
199    
200     tlb_miss:
201     expevt = wf? EXPEVT_TLB_MISS_ST : EXPEVT_TLB_MISS_LD;
202     goto exception;
203    
204     protection_violation:
205     expevt = wf? EXPEVT_TLB_PROT_ST : EXPEVT_TLB_PROT_LD;
206     goto exception;
207    
208     initial_write_exception:
209     expevt = EXPEVT_TLB_MOD;
210    
211    
212     exception:
213     if (flags & FLAG_NOEXCEPTIONS) {
214     *return_paddr = 0;
215     return 2;
216     }
217    
218     sh_exception(cpu, expevt, 0, vaddr);
219    
220     return 0;
221 dpavlin 30 }
222    
223 dpavlin 32
224     /*
225     * sh_translate_v2p():
226     *
227     * Return values:
228     *
229     * 0 No access to the virtual address.
230     * 1 return_paddr contains the physical address, the page is
231     * available as read-only.
232     * 2 Same as 1, but the page is available as read/write.
233     */
234     int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_paddr,
235     int flags)
236     {
237     int user = cpu->cd.sh.sr & SH_SR_MD? 0 : 1;
238    
239     vaddr = (uint32_t)vaddr;
240    
241     /* U0/P0: Userspace addresses, or P3: Kernel virtual memory. */
242     if (!(vaddr & 0x80000000) ||
243     (vaddr >= 0xc0000000 && vaddr < 0xe0000000)) {
244     /* Address translation turned off? */
245     if (!(cpu->cd.sh.mmucr & SH4_MMUCR_AT)) {
246     /* Then return raw physical address: */
247     *return_paddr = vaddr & 0x1fffffff;
248     return 2;
249     }
250    
251     /* Perform translation via the MMU: */
252     return translate_via_mmu(cpu, vaddr, return_paddr, flags);
253     }
254    
255     /* Store queue region: */
256     if (vaddr >= 0xe0000000 && vaddr < 0xe4000000) {
257     /* Note/TODO: Take SH4_MMUCR_SQMD into account. */
258     *return_paddr = vaddr;
259     return 2;
260     }
261    
262     if (user) {
263     if (flags & FLAG_NOEXCEPTIONS) {
264     *return_paddr = 0;
265     return 2;
266     }
267    
268     fatal("Userspace tried to access non-user space memory."
269     " TODO: cause exception! (vaddr=0x%08"PRIx32"\n",
270     (uint32_t) vaddr);
271     exit(1);
272     }
273    
274     /* P1,P2: Direct-mapped physical memory. */
275     if (vaddr >= 0x80000000 && vaddr < 0xc0000000) {
276     *return_paddr = vaddr & 0x1fffffff;
277     return 2;
278     }
279    
280     if (flags & FLAG_INSTR) {
281     fatal("TODO: instr at 0x%08"PRIx32"\n", (uint32_t)vaddr);
282     exit(1);
283     }
284    
285     /* P4: Special registers mapped at 0xf0000000 .. 0xffffffff: */
286     if ((vaddr & 0xf0000000) == 0xf0000000) {
287     *return_paddr = vaddr;
288     return 2;
289     }
290    
291     if (flags & FLAG_NOEXCEPTIONS) {
292     *return_paddr = 0;
293     return 2;
294     }
295    
296     /* TODO */
297     fatal("Unimplemented SH vaddr 0x%08"PRIx32"\n", (uint32_t)vaddr);
298     exit(1);
299     }
300    

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