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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_ppc.c,v 1.27 2006/12/30 13:30:56 debug Exp $ |
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* |
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* Included from cpu_ppc.c. |
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*/ |
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|
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|
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#include "ppc_bat.h" |
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#include "ppc_pte.h" |
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|
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|
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/* |
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* ppc_bat(): |
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* |
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* BAT translation. Returns -1 if there was no BAT hit, >= 0 for a hit. |
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* (0 for access denied, 1 for read-only, and 2 for read-write access allowed.) |
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*/ |
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int ppc_bat(struct cpu *cpu, uint64_t vaddr, uint64_t *return_paddr, int flags, |
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int user) |
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{ |
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int i, istart = 0, iend = 8, pp; |
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|
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if (flags & FLAG_INSTR) |
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iend = 4; |
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else |
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istart = 4; |
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|
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if (cpu->cd.ppc.bits != 32) { |
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fatal("TODO: ppc_bat() for non-32-bit\n"); |
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exit(1); |
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} |
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if (cpu->cd.ppc.cpu_type.flags & PPC_601) { |
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fatal("TODO: ppc_bat() for PPC 601\n"); |
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exit(1); |
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} |
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|
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/* Scan either the 4 instruction BATs or the 4 data BATs: */ |
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for (i=istart; i<iend; i++) { |
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int regnr = SPR_IBAT0U + i * 2; |
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uint32_t upper = cpu->cd.ppc.spr[regnr]; |
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uint32_t lower = cpu->cd.ppc.spr[regnr + 1]; |
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uint32_t phys = lower & BAT_RPN, ebs = upper & BAT_EPI; |
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uint32_t mask = ((upper & BAT_BL) << 15) | 0x1ffff; |
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|
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/* Not valid in either supervisor or user mode? */ |
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if (user && !(upper & BAT_Vu)) |
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continue; |
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if (!user && !(upper & BAT_Vs)) |
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continue; |
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|
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/* Virtual address mismatch? Then skip. */ |
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if ((vaddr & ~mask) != (ebs & ~mask)) |
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continue; |
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|
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*return_paddr = (vaddr & mask) | (phys & ~mask); |
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|
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pp = lower & BAT_PP; |
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switch (pp) { |
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case BAT_PP_NONE: |
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return 0; |
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case BAT_PP_RO_S: |
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case BAT_PP_RO: |
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return (flags & FLAG_WRITEFLAG)? 0 : 1; |
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default:/* BAT_PP_RW: */ |
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return 2; |
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} |
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} |
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|
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return -1; |
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} |
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|
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|
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/* |
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* get_pte_low(): |
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* |
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* Scan a PTE group for a cmp (compare) value. |
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* |
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* Returns 1 if the value was found, and *lowp is set to the low PTE word. |
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* Returns 0 if no match was found. |
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*/ |
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static int get_pte_low(struct cpu *cpu, uint64_t pteg_select, |
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uint32_t *lowp, uint32_t cmp) |
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{ |
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unsigned char *d = memory_paddr_to_hostaddr(cpu->mem, pteg_select, 1); |
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int i; |
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|
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for (i=0; i<8; i++) { |
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uint32_t *ep = (uint32_t *) (d + (i << 3)), upper; |
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upper = *ep; |
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upper = BE32_TO_HOST(upper); |
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|
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/* Valid PTE, and correct api and vsid? */ |
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if (upper == cmp) { |
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uint32_t lo = ep[1]; |
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lo = BE32_TO_HOST(lo); |
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*lowp = lo; |
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return 1; |
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} |
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} |
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|
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return 0; |
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} |
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|
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|
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/* |
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* ppc_vtp32(): |
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* |
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* Virtual to physical address translation (32-bit mode). |
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* |
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* Returns 1 if a translation was found, 0 if none was found. However, finding |
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* a translation does not mean that it should be returned; there can be |
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* a permission violation. *resp is set to 0 for no access, 1 for read-only |
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* access, or 2 for read/write access. |
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*/ |
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static int ppc_vtp32(struct cpu *cpu, uint32_t vaddr, uint64_t *return_paddr, |
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int *resp, uint64_t msr, int writeflag, int instr) |
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{ |
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int srn = (vaddr >> 28) & 15, api = (vaddr >> 22) & PTE_API; |
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int access, key, match; |
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uint32_t vsid = cpu->cd.ppc.sr[srn] & 0x00ffffff; |
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uint64_t sdr1 = cpu->cd.ppc.spr[SPR_SDR1], htaborg; |
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uint32_t hash1, hash2, pteg_select, tmp; |
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uint32_t lower_pte = 0, cmp; |
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|
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htaborg = sdr1 & 0xffff0000UL; |
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|
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/* Primary hash: */ |
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hash1 = (vsid & 0x7ffff) ^ ((vaddr >> 12) & 0xffff); |
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tmp = (hash1 >> 10) & (sdr1 & 0x1ff); |
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pteg_select = htaborg & 0xfe000000; |
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pteg_select |= ((hash1 & 0x3ff) << 6); |
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pteg_select |= (htaborg & 0x01ff0000) | (tmp << 16); |
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cpu->cd.ppc.spr[SPR_HASH1] = pteg_select; |
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cmp = cpu->cd.ppc.spr[instr? SPR_ICMP : SPR_DCMP] = |
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PTE_VALID | api | (vsid << PTE_VSID_SHFT); |
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match = get_pte_low(cpu, pteg_select, &lower_pte, cmp); |
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|
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/* Secondary hash: */ |
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hash2 = hash1 ^ 0x7ffff; |
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tmp = (hash2 >> 10) & (sdr1 & 0x1ff); |
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pteg_select = htaborg & 0xfe000000; |
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pteg_select |= ((hash2 & 0x3ff) << 6); |
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pteg_select |= (htaborg & 0x01ff0000) | (tmp << 16); |
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cpu->cd.ppc.spr[SPR_HASH2] = pteg_select; |
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if (!match) { |
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cmp |= PTE_HID; |
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match = get_pte_low(cpu, pteg_select, &lower_pte, cmp); |
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} |
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|
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*resp = 0; |
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|
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if (!match) |
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return 0; |
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|
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/* Non-executable, or Guarded page? */ |
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if (instr && cpu->cd.ppc.sr[srn] & SR_NOEXEC) |
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return 1; |
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if (instr && lower_pte & PTE_G) |
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return 1; |
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|
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access = lower_pte & PTE_PP; |
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*return_paddr = (lower_pte & PTE_RPGN) | (vaddr & ~PTE_RPGN); |
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|
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key = (cpu->cd.ppc.sr[srn] & SR_PRKEY && msr & PPC_MSR_PR) || |
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(cpu->cd.ppc.sr[srn] & SR_SUKEY && !(msr & PPC_MSR_PR)); |
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|
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if (key) { |
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switch (access) { |
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case 1: |
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case 3: *resp = writeflag? 0 : 1; |
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break; |
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case 2: *resp = 2; |
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break; |
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} |
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} else { |
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switch (access) { |
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case 3: *resp = writeflag? 0 : 1; |
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break; |
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default:*resp = 2; |
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} |
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} |
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|
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return 1; |
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} |
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|
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|
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/* |
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* ppc_translate_v2p(): |
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* |
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* Don't call this function if userland_emul is non-NULL, or cpu is NULL. |
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* |
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* Return values: |
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* 0 Failure |
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* 1 Success, the page is readable only |
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* 2 Success, the page is read/write |
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*/ |
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int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_paddr, int flags) |
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{ |
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int instr = flags & FLAG_INSTR, res = 0, match, user; |
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int writeflag = flags & FLAG_WRITEFLAG? 1 : 0; |
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uint64_t msr; |
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|
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reg_access_msr(cpu, &msr, 0, 0); |
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user = msr & PPC_MSR_PR? 1 : 0; |
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|
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if (cpu->cd.ppc.bits == 32) |
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vaddr &= 0xffffffff; |
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|
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if ((instr && !(msr & PPC_MSR_IR)) || (!instr && !(msr & PPC_MSR_DR))) { |
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*return_paddr = vaddr; |
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return 2; |
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} |
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|
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if (cpu->cd.ppc.cpu_type.flags & PPC_601) { |
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fatal("ppc_translate_v2p(): TODO: 601\n"); |
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exit(1); |
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} |
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|
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/* Try the BATs first: */ |
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if (cpu->cd.ppc.bits == 32) { |
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res = ppc_bat(cpu, vaddr, return_paddr, flags, user); |
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if (res > 0) |
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return res; |
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if (res == 0) { |
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fatal("[ TODO: BAT exception ]\n"); |
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exit(1); |
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} |
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} |
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|
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/* Virtual to physical translation: */ |
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if (cpu->cd.ppc.bits == 32) { |
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match = ppc_vtp32(cpu, vaddr, return_paddr, &res, msr, |
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writeflag, instr); |
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if (match && res > 0) |
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return res; |
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} else { |
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/* htaborg = sdr1 & 0xfffffffffffc0000ULL; */ |
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fatal("TODO: ppc 64-bit translation\n"); |
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exit(1); |
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} |
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|
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|
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/* |
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* No match? Then cause an exception. |
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* |
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* PPC603: cause a software TLB reload exception. |
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* All others: cause a DSI or ISI. |
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*/ |
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|
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if (flags & FLAG_NOEXCEPTIONS) |
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return 0; |
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|
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if (!quiet_mode) |
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fatal("[ memory_ppc: exception! vaddr=0x%"PRIx64" pc=0x%"PRIx64 |
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" instr=%i user=%i wf=%i ]\n", (uint64_t) vaddr, |
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(uint64_t) cpu->pc, instr, user, writeflag); |
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exit(1); |
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|
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if (cpu->cd.ppc.cpu_type.flags & PPC_603) { |
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cpu->cd.ppc.spr[instr? SPR_IMISS : SPR_DMISS] = vaddr; |
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|
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msr |= PPC_MSR_TGPR; |
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reg_access_msr(cpu, &msr, 1, 0); |
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|
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ppc_exception(cpu, instr? 0x10 : (writeflag? 0x12 : 0x11)); |
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} else { |
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if (!instr) { |
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cpu->cd.ppc.spr[SPR_DAR] = vaddr; |
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cpu->cd.ppc.spr[SPR_DSISR] = match? |
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DSISR_PROTECT : DSISR_NOTFOUND; |
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if (writeflag) |
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cpu->cd.ppc.spr[SPR_DSISR] |= DSISR_STORE; |
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} |
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ppc_exception(cpu, instr? |
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PPC_EXCEPTION_ISI : PPC_EXCEPTION_DSI); |
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} |
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|
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return 0; |
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} |
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|