/[gxemul]/trunk/src/cpus/memory_ppc.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/memory_ppc.c

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Revision 24 - (hide annotations)
Mon Oct 8 16:19:56 2007 UTC (11 years, 11 months ago) by dpavlin
File MIME type: text/plain
File size: 8272 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 dpavlin 14 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 24 * $Id: memory_ppc.c,v 1.23 2006/03/30 19:41:51 debug Exp $
29 dpavlin 14 *
30     * Included from cpu_ppc.c.
31     */
32    
33    
34 dpavlin 20 #include "ppc_bat.h"
35     #include "ppc_pte.h"
36    
37    
38 dpavlin 14 /*
39 dpavlin 20 * ppc_bat():
40     *
41     * BAT translation. Returns -1 if there was no BAT hit, >= 0 for a hit.
42     * (0 for access denied, 1 for read-only, and 2 for read-write access allowed.)
43     */
44     int ppc_bat(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags,
45     int user)
46     {
47 dpavlin 22 int i, istart = 0, iend = 8, pp;
48 dpavlin 20
49 dpavlin 22 if (flags & FLAG_INSTR)
50     iend = 4;
51     else
52     istart = 4;
53    
54 dpavlin 20 if (cpu->cd.ppc.bits != 32) {
55     fatal("TODO: ppc_bat() for non-32-bit\n");
56     exit(1);
57     }
58     if (cpu->cd.ppc.cpu_type.flags & PPC_601) {
59     fatal("TODO: ppc_bat() for PPC 601\n");
60     exit(1);
61     }
62    
63 dpavlin 22 /* Scan either the 4 instruction BATs or the 4 data BATs: */
64     for (i=istart; i<iend; i++) {
65     int regnr = SPR_IBAT0U + i * 2;
66 dpavlin 20 uint32_t upper = cpu->cd.ppc.spr[regnr];
67     uint32_t lower = cpu->cd.ppc.spr[regnr + 1];
68     uint32_t phys = lower & BAT_RPN, ebs = upper & BAT_EPI;
69     uint32_t mask = ((upper & BAT_BL) << 15) | 0x1ffff;
70    
71     /* Not valid in either supervisor or user mode? */
72     if (user && !(upper & BAT_Vu))
73     continue;
74     if (!user && !(upper & BAT_Vs))
75     continue;
76    
77     /* Virtual address mismatch? Then skip. */
78     if ((vaddr & ~mask) != (ebs & ~mask))
79     continue;
80    
81     *return_addr = (vaddr & mask) | (phys & ~mask);
82    
83     pp = lower & BAT_PP;
84     switch (pp) {
85     case BAT_PP_NONE:
86     return 0;
87     case BAT_PP_RO_S:
88     case BAT_PP_RO:
89     return (flags & FLAG_WRITEFLAG)? 0 : 1;
90     default:/* BAT_PP_RW: */
91     return 2;
92     }
93     }
94    
95     return -1;
96     }
97    
98    
99     /*
100     * get_pte_low():
101     *
102     * Scan a PTE group for a cmp (compare) value.
103     *
104     * Returns 1 if the value was found, and *lowp is set to the low PTE word.
105     * Returns 0 if no match was found.
106     */
107     static int get_pte_low(struct cpu *cpu, uint64_t pteg_select,
108     uint32_t *lowp, uint32_t cmp)
109     {
110 dpavlin 22 unsigned char *d = memory_paddr_to_hostaddr(cpu->mem, pteg_select, 1)
111     + (pteg_select & ((1 << BITS_PER_MEMBLOCK) - 1));
112 dpavlin 20 int i;
113    
114     for (i=0; i<8; i++) {
115 dpavlin 22 uint32_t *ep = (uint32_t *) (d + (i << 3)), upper;
116     upper = *ep;
117     upper = BE32_TO_HOST(upper);
118 dpavlin 20
119     /* Valid PTE, and correct api and vsid? */
120     if (upper == cmp) {
121 dpavlin 22 uint32_t lo = ep[1];
122     lo = BE32_TO_HOST(lo);
123     *lowp = lo;
124 dpavlin 20 return 1;
125     }
126     }
127    
128     return 0;
129     }
130    
131    
132     /*
133     * ppc_vtp32():
134     *
135     * Virtual to physical address translation (32-bit mode).
136     *
137     * Returns 1 if a translation was found, 0 if none was found. However, finding
138     * a translation does not mean that it should be returned; there can be
139     * a permission violation. *resp is set to 0 for no access, 1 for read-only
140     * access, or 2 for read/write access.
141     */
142     static int ppc_vtp32(struct cpu *cpu, uint32_t vaddr, uint64_t *return_addr,
143     int *resp, uint64_t msr, int writeflag, int instr)
144     {
145     int srn = (vaddr >> 28) & 15, api = (vaddr >> 22) & PTE_API;
146     int access, key, match;
147     uint32_t vsid = cpu->cd.ppc.sr[srn] & 0x00ffffff;
148     uint64_t sdr1 = cpu->cd.ppc.spr[SPR_SDR1], htaborg;
149     uint32_t hash1, hash2, pteg_select, tmp;
150     uint32_t lower_pte = 0, cmp;
151    
152     htaborg = sdr1 & 0xffff0000UL;
153    
154     /* Primary hash: */
155     hash1 = (vsid & 0x7ffff) ^ ((vaddr >> 12) & 0xffff);
156     tmp = (hash1 >> 10) & (sdr1 & 0x1ff);
157     pteg_select = htaborg & 0xfe000000;
158     pteg_select |= ((hash1 & 0x3ff) << 6);
159     pteg_select |= (htaborg & 0x01ff0000) | (tmp << 16);
160     cpu->cd.ppc.spr[SPR_HASH1] = pteg_select;
161     cmp = cpu->cd.ppc.spr[instr? SPR_ICMP : SPR_DCMP] =
162     PTE_VALID | api | (vsid << PTE_VSID_SHFT);
163     match = get_pte_low(cpu, pteg_select, &lower_pte, cmp);
164    
165     /* Secondary hash: */
166     hash2 = hash1 ^ 0x7ffff;
167     tmp = (hash2 >> 10) & (sdr1 & 0x1ff);
168     pteg_select = htaborg & 0xfe000000;
169     pteg_select |= ((hash2 & 0x3ff) << 6);
170     pteg_select |= (htaborg & 0x01ff0000) | (tmp << 16);
171     cpu->cd.ppc.spr[SPR_HASH2] = pteg_select;
172     if (!match) {
173     cmp |= PTE_HID;
174     match = get_pte_low(cpu, pteg_select, &lower_pte, cmp);
175     }
176    
177     *resp = 0;
178    
179     if (!match)
180     return 0;
181    
182     /* Non-executable, or Guarded page? */
183     if (instr && cpu->cd.ppc.sr[srn] & SR_NOEXEC)
184     return 1;
185     if (instr && lower_pte & PTE_G)
186     return 1;
187    
188     access = lower_pte & PTE_PP;
189     *return_addr = (lower_pte & PTE_RPGN) | (vaddr & ~PTE_RPGN);
190    
191     key = (cpu->cd.ppc.sr[srn] & SR_PRKEY && msr & PPC_MSR_PR) ||
192     (cpu->cd.ppc.sr[srn] & SR_SUKEY && !(msr & PPC_MSR_PR));
193    
194     if (key) {
195     switch (access) {
196     case 1:
197     case 3: *resp = writeflag? 0 : 1;
198     break;
199     case 2: *resp = 2;
200     break;
201     }
202     } else {
203     switch (access) {
204     case 3: *resp = writeflag? 0 : 1;
205     break;
206     default:*resp = 2;
207     }
208     }
209    
210     return 1;
211     }
212    
213    
214     /*
215 dpavlin 14 * ppc_translate_address():
216     *
217     * Don't call this function is userland_emul is non-NULL, or cpu is NULL.
218     *
219     * Return values:
220     * 0 Failure
221     * 1 Success, the page is readable only
222     * 2 Success, the page is read/write
223     */
224     int ppc_translate_address(struct cpu *cpu, uint64_t vaddr,
225     uint64_t *return_addr, int flags)
226     {
227 dpavlin 20 int instr = flags & FLAG_INSTR, res = 0, match, user;
228     int writeflag = flags & FLAG_WRITEFLAG? 1 : 0;
229     uint64_t msr;
230 dpavlin 14
231 dpavlin 20 reg_access_msr(cpu, &msr, 0, 0);
232     user = msr & PPC_MSR_PR? 1 : 0;
233    
234 dpavlin 14 if (cpu->cd.ppc.bits == 32)
235     vaddr &= 0xffffffff;
236    
237 dpavlin 20 if ((instr && !(msr & PPC_MSR_IR)) || (!instr && !(msr & PPC_MSR_DR))) {
238 dpavlin 14 *return_addr = vaddr;
239     return 2;
240     }
241    
242 dpavlin 20 if (cpu->cd.ppc.cpu_type.flags & PPC_601) {
243     fatal("ppc_translate_address(): TODO: 601\n");
244     exit(1);
245     }
246 dpavlin 14
247 dpavlin 20 /* Try the BATs first: */
248     if (cpu->cd.ppc.bits == 32) {
249     res = ppc_bat(cpu, vaddr, return_addr, flags, user);
250     if (res > 0)
251     return res;
252     if (res == 0) {
253     fatal("[ TODO: BAT exception ]\n");
254     exit(1);
255 dpavlin 14 }
256 dpavlin 20 }
257 dpavlin 14
258 dpavlin 20 /* Virtual to physical translation: */
259     if (cpu->cd.ppc.bits == 32) {
260     match = ppc_vtp32(cpu, vaddr, return_addr, &res, msr,
261     writeflag, instr);
262     if (match && res > 0)
263     return res;
264     } else {
265     /* htaborg = sdr1 & 0xfffffffffffc0000ULL; */
266     fatal("TODO: ppc 64-bit translation\n");
267     exit(1);
268 dpavlin 14 }
269    
270 dpavlin 20
271     /*
272     * No match? Then cause an exception.
273     *
274     * PPC603: cause a software TLB reload exception.
275     * All others: cause a DSI or ISI.
276     */
277    
278 dpavlin 14 if (flags & FLAG_NOEXCEPTIONS)
279     return 0;
280    
281 dpavlin 20 if (!quiet_mode)
282 dpavlin 24 fatal("[ memory_ppc: exception! vaddr=0x%"PRIx64" pc=0x%"PRIx64
283     " instr=%i user=%i wf=%i ]\n", (uint64_t) vaddr,
284     (uint64_t) cpu->pc, instr, user, writeflag);
285 dpavlin 20
286     if (cpu->cd.ppc.cpu_type.flags & PPC_603) {
287     cpu->cd.ppc.spr[instr? SPR_IMISS : SPR_DMISS] = vaddr;
288    
289     msr |= PPC_MSR_TGPR;
290     reg_access_msr(cpu, &msr, 1, 0);
291    
292     ppc_exception(cpu, instr? 0x10 : (writeflag? 0x12 : 0x11));
293     } else {
294     if (!instr) {
295     cpu->cd.ppc.spr[SPR_DAR] = vaddr;
296     cpu->cd.ppc.spr[SPR_DSISR] = match?
297     DSISR_PROTECT : DSISR_NOTFOUND;
298     if (writeflag)
299     cpu->cd.ppc.spr[SPR_DSISR] |= DSISR_STORE;
300     }
301     ppc_exception(cpu, instr?
302     PPC_EXCEPTION_ISI : PPC_EXCEPTION_DSI);
303     }
304    
305 dpavlin 14 return 0;
306     }
307    

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