25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: memory_mips_v2p.c,v 1.3 2005/12/26 12:32:10 debug Exp $ |
* $Id: memory_mips_v2p.c,v 1.6 2006/06/24 21:47:23 debug Exp $ |
29 |
* |
* |
30 |
* Included from memory.c. |
* Included from memory.c. |
31 |
*/ |
*/ |
32 |
|
|
33 |
|
|
34 |
/* |
/* |
35 |
* translate_address(): |
* translate_v2p(): |
36 |
* |
* |
37 |
* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
38 |
* |
* |
44 |
* 2 Success, the page is read/write |
* 2 Success, the page is read/write |
45 |
*/ |
*/ |
46 |
int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr, |
int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr, |
47 |
uint64_t *return_addr, int flags) |
uint64_t *return_paddr, int flags) |
48 |
{ |
{ |
49 |
int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ; |
int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ; |
50 |
int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
|
int instr = flags & FLAG_INSTR; |
|
51 |
int ksu, use_tlb, status, i; |
int ksu, use_tlb, status, i; |
52 |
uint64_t vaddr_vpn2=0, vaddr_asid=0; |
uint64_t vaddr_vpn2=0, vaddr_asid=0; |
53 |
int exccode, tlb_refill; |
int exccode, tlb_refill; |
54 |
struct mips_coproc *cp0; |
struct mips_coproc *cp0; |
|
int bintrans_cached = cpu->machine->bintrans_enable; |
|
55 |
|
|
56 |
#ifdef V2P_MMU3K |
#ifdef V2P_MMU3K |
57 |
const int x_64 = 0; |
const int x_64 = 0; |
83 |
#endif /* !V2P_MMU3K */ |
#endif /* !V2P_MMU3K */ |
84 |
|
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85 |
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#ifdef USE_TINY_CACHE |
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/* |
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* Check the tiny translation cache first: |
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* |
|
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* Only userland addresses are checked, because other addresses |
|
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* are probably better of being statically translated, or through |
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* the TLB. (Note: When running with 64-bit addresses, this |
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* will still produce the correct result. At worst, we check the |
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* cache in vain, but the result should still be correct.) |
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*/ |
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if (!bintrans_cached && |
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(vaddr & 0xc0000000ULL) != 0x80000000ULL) { |
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int i, wf = 1 + (writeflag == MEM_WRITE); |
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uint64_t vaddr_shift_12 = vaddr >> 12; |
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if (instr) { |
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/* Code: */ |
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for (i=0; i<N_TRANSLATION_CACHE_INSTR; i++) { |
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if (cpu->cd.mips.translation_cache_instr[i].wf |
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>= wf && vaddr_shift_12 == (cpu->cd.mips. |
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translation_cache_instr[i].vaddr_pfn)) { |
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*return_addr = cpu->cd.mips. |
|
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translation_cache_instr[i].paddr |
|
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| (vaddr & 0xfff); |
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return cpu->cd.mips. |
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translation_cache_instr[i].wf; |
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} |
|
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} |
|
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} else { |
|
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/* Data: */ |
|
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for (i=0; i<N_TRANSLATION_CACHE_DATA; i++) { |
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if (cpu->cd.mips.translation_cache_data[i].wf |
|
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>= wf && vaddr_shift_12 == (cpu->cd.mips. |
|
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translation_cache_data[i].vaddr_pfn)) { |
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*return_addr = cpu->cd.mips. |
|
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translation_cache_data[i].paddr |
|
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| (vaddr & 0xfff); |
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return cpu->cd.mips. |
|
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translation_cache_data[i].wf; |
|
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} |
|
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} |
|
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} |
|
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} |
|
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#endif |
|
|
|
|
86 |
exccode = -1; |
exccode = -1; |
87 |
tlb_refill = 1; |
tlb_refill = 1; |
88 |
|
|
195 |
* On IP27 (and probably others), addresses such as |
* On IP27 (and probably others), addresses such as |
196 |
* 0x92... and 0x96... have to do with NUMA stuff. |
* 0x92... and 0x96... have to do with NUMA stuff. |
197 |
*/ |
*/ |
198 |
*return_addr = vaddr & (((uint64_t)1 << 44) - 1); |
*return_paddr = vaddr & (((uint64_t)1 << 44) - 1); |
199 |
return 2; |
return 2; |
200 |
} |
} |
201 |
|
|
219 |
/* kseg0, kseg1: */ |
/* kseg0, kseg1: */ |
220 |
if (vaddr >= (uint64_t)0xffffffff80000000ULL && |
if (vaddr >= (uint64_t)0xffffffff80000000ULL && |
221 |
vaddr <= (uint64_t)0xffffffffbfffffffULL) { |
vaddr <= (uint64_t)0xffffffffbfffffffULL) { |
222 |
*return_addr = vaddr & 0x1fffffff; |
*return_paddr = vaddr & 0x1fffffff; |
223 |
return 2; |
return 2; |
224 |
} |
} |
225 |
|
|
332 |
/* Is there a VPN and ASID match? */ |
/* Is there a VPN and ASID match? */ |
333 |
if (entry_vpn2 == vaddr_vpn2 && |
if (entry_vpn2 == vaddr_vpn2 && |
334 |
(entry_asid == vaddr_asid || g_bit)) { |
(entry_asid == vaddr_asid || g_bit)) { |
335 |
/* debug("OK MAP 1, i=%i { vaddr=%016llx " |
/* debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" " |
336 |
"==> paddr %016llx v=%i d=%i " |
"==> paddr %016"PRIx64" v=%i d=%i " |
337 |
"asid=0x%02x }\n", i, (long long)vaddr, |
"asid=0x%02x }\n", i, (uint64_t) vaddr, |
338 |
(long long) *return_addr, v_bit?1:0, |
(uint64_t) *return_paddr, v_bit?1:0, |
339 |
d_bit?1:0, vaddr_asid); */ |
d_bit?1:0, vaddr_asid); */ |
340 |
if (v_bit) { |
if (v_bit) { |
341 |
if (d_bit || (!d_bit && |
if (d_bit || (!d_bit && |
342 |
writeflag == MEM_READ)) { |
writeflag == MEM_READ)) { |
343 |
uint64_t paddr; |
uint64_t paddr; |
344 |
/* debug("OK MAP 2!!! { w=%i " |
/* debug("OK MAP 2!!! { w=%i " |
345 |
"vaddr=%016llx ==> d=%i v=" |
"vaddr=%016"PRIx64" ==> " |
346 |
"%i paddr %016llx ", |
"d=%i v=%i paddr %016" |
347 |
writeflag, (long long)vaddr, |
PRIx64" ", |
348 |
|
writeflag, (uint64_t)vaddr, |
349 |
d_bit?1:0, v_bit?1:0, |
d_bit?1:0, v_bit?1:0, |
350 |
(long long) *return_addr); |
(uint64_t) *return_paddr); |
351 |
debug(", tlb entry %2i: ma" |
debug(", tlb entry %2i: ma" |
352 |
"sk=%016llx hi=%016llx lo0" |
"sk=%016"PRIx64" hi=%016" |
353 |
"=%016llx lo1=%016llx\n", |
PRIx64" lo0=%016"PRIx64 |
354 |
|
" lo1=%016"PRIx64"\n", |
355 |
i, cp0->tlbs[i].mask, cp0-> |
i, cp0->tlbs[i].mask, cp0-> |
356 |
tlbs[i].hi, cp0->tlbs[i]. |
tlbs[i].hi, cp0->tlbs[i]. |
357 |
lo0, cp0->tlbs[i].lo1); |
lo0, cp0->tlbs[i].lo1); |
369 |
(vaddr & pmask); |
(vaddr & pmask); |
370 |
#endif |
#endif |
371 |
|
|
372 |
/* |
*return_paddr = paddr; |
|
* Enter into the tiny trans- |
|
|
* lation cache (if enabled) |
|
|
* and return: |
|
|
*/ |
|
|
if (!bintrans_cached) |
|
|
insert_into_tiny_cache( |
|
|
cpu, instr, d_bit? |
|
|
MEM_WRITE : |
|
|
MEM_READ, |
|
|
vaddr, paddr); |
|
|
|
|
|
*return_addr = paddr; |
|
373 |
return d_bit? 2 : 1; |
return d_bit? 2 : 1; |
374 |
} else { |
} else { |
375 |
/* TLB modif. exception */ |
/* TLB modif. exception */ |