/[gxemul]/trunk/src/cpus/memory_mips_v2p.c
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Contents of /trunk/src/cpus/memory_mips_v2p.c

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 13889 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============
1 /*
2 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: memory_mips_v2p.c,v 1.14 2006/10/14 23:47:37 debug Exp $
29 */
30
31
32 /*
33 * translate_v2p():
34 *
35 * Translate a virtual MIPS address to a physical address, by looking up the
36 * address in the TLB. On failure, an exception is generated (except for the
37 * case when FLAG_NOEXCEPTIONS is used).
38 *
39 * Note: This function is long and hairy, it is included several times with
40 * various defines set, to produce more or less optimized versions of
41 * the function for different emulated CPU types.
42 *
43 * V2P_MMU3K Defined for R2000/R3000 emulation. If it is not defined,
44 * R4000+/MIPS32/MIPS64 is presumed.
45 * V2P_MMU10K This enables the use of 44 userspace bits, instead of 40.
46 * V2P_MMU4100 VR41xx processors support 1 KB pages, so their page mask
47 * is slightly different. (The emulator only supports 4 KB
48 * pages, though.)
49 * V2P_MMU8K Not yet. (TODO.)
50 *
51 *
52 * Note: Unfortunately, the variable name vpn2 is poorly choosen for R2K/R3K,
53 * since it actual contains the vpn.
54 *
55 * Return values:
56 * 0 Failure
57 * 1 Success, the page is readable only
58 * 2 Success, the page is read/write
59 */
60 int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr,
61 uint64_t *return_paddr, int flags)
62 {
63 int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ;
64 int no_exceptions = flags & FLAG_NOEXCEPTIONS;
65 int ksu, use_tlb, status, i;
66 uint64_t vaddr_vpn2=0, vaddr_asid=0;
67 int exccode, tlb_refill;
68 struct mips_coproc *cp0;
69
70 #ifdef V2P_MMU3K
71 const int x_64 = 0;
72 const int n_tlbs = 64;
73 const int pmask = 0xfff;
74 uint64_t xuseg_top; /* Well, useg actually. */
75 #else
76 #ifdef V2P_MMU10K
77 const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K;
78 uint64_t xuseg_top = ENTRYHI_VPN2_MASK_R10K | 0x1fffULL;
79 #else
80 #ifdef V2P_MMU4100
81 const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800;
82 #else
83 const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK;
84 #endif
85 uint64_t xuseg_top = ENTRYHI_VPN2_MASK | 0x1fffULL;
86 #endif
87 int x_64; /* non-zero for 64-bit address space accesses */
88 int pageshift, n_tlbs;
89 int pmask;
90 #ifdef V2P_MMU4100
91 const int pagemask_mask = PAGEMASK_MASK_R4100;
92 const int pagemask_shift = PAGEMASK_SHIFT_R4100;
93 const int pfn_shift = 10;
94 #else
95 const int pagemask_mask = PAGEMASK_MASK;
96 const int pagemask_shift = PAGEMASK_SHIFT;
97 const int pfn_shift = 12;
98 #endif
99 #endif /* !V2P_MMU3K */
100
101
102 exccode = -1;
103 tlb_refill = 1;
104
105 /* Cached values: */
106 cp0 = cpu->cd.mips.coproc[0];
107 status = cp0->reg[COP0_STATUS];
108
109 /*
110 * MIPS R4000+ and MIPS64 Address Translation:
111 *
112 * An address may be in one of the kernel segments, that are directly
113 * mapped to physical addresses, or the address needs to be looked up
114 * in the TLB entries.
115 *
116 * KSU: EXL: ERL: X: Name: Range:
117 * ---- ---- ---- -- ----- ------
118 *
119 * 10 0 0 0 useg 0 - 0x7fffffff (2GB) (via TLB)
120 * 10 0 0 1 xuseg 0 - 0xffffffffff (1TB) (via TLB)
121 *
122 * 01 0 0 0 suseg 0 - 0x7fffffff (2GB via TLB)
123 * 01 0 0 0 ssseg 0xc0000000 - 0xdfffffff (0.5 GB via TLB)
124 * 01 0 0 1 xsuseg 0 - 0xffffffffff (1TB) (via TLB)
125 * 01 0 0 1 xsseg 0x4000000000000000 - 0x400000ffffffffff
126 * (1TB) (via TLB)
127 * 01 0 0 1 csseg 0xffffffffc0000000 - 0xffffffffdfffffff
128 * (0.5TB) (via TLB)
129 *
130 * 00 x x 0 kuseg 0 - 0x7fffffff (2GB) (via TLB) (*)
131 * 00 x x 0 kseg0 0x80000000 - 0x9fffffff (0.5GB)
132 * unmapped, cached
133 * 00 x x 0 kseg1 0xa0000000 - 0xbfffffff (0.5GB)
134 * unmapped, uncached
135 * 00 x x 0 ksseg 0xc0000000 - 0xdfffffff (0.5GB) (via TLB)
136 * 00 x x 0 kseg3 0xe0000000 - 0xffffffff (0.5GB) (via TLB)
137 * 00 x x 1 xksuseg 0 - 0xffffffffff (1TB) (via TLB) (*)
138 * 00 x x 1 xksseg 0x4000000000000000 - 0x400000ffffffffff
139 * (1TB) (via TLB)
140 * 00 x x 1 xkphys 0x8000000000000000 - 0xbfffffffffffffff
141 * 00 x x 1 xkseg 0xc000000000000000 - 0xc00000ff7fffffff
142 * 00 x x 1 ckseg0 0xffffffff80000000 - 0xffffffff9fffffff
143 * 00 x x 1 ckseg1 0xffffffffa0000000 - 0xffffffffbfffffff
144 * 00 x x 1 cksseg 0xffffffffc0000000 - 0xffffffffdfffffff
145 * 00 x x 1 ckseg3 0xffffffffe0000000 - 0xffffffffffffffff
146 * like 0x80000000 - 0xffffffff
147 *
148 * (*) = if ERL=1 then kuseg is not via TLB, but unmapped,
149 * uncached physical memory.
150 *
151 * (KSU==0 or EXL=1 or ERL=1 is enough to use k*seg*.)
152 *
153 * An invalid address causes an Address Error.
154 *
155 * See chapter 4, page 96, in the R4000 manual for more info!
156 */
157
158 #ifdef V2P_MMU3K
159 if (status & MIPS1_SR_KU_CUR)
160 ksu = KSU_USER;
161 else
162 ksu = KSU_KERNEL;
163
164 /* These are needed later: */
165 vaddr_asid = cp0->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK;
166 vaddr_vpn2 = vaddr & R2K3K_ENTRYHI_VPN_MASK;
167 #else
168 /* kx,sx,ux = 0 for 32-bit addressing, 1 for 64-bit addressing. */
169 ksu = (status & STATUS_KSU_MASK) >> STATUS_KSU_SHIFT;
170 if (status & (STATUS_EXL | STATUS_ERL))
171 ksu = KSU_KERNEL;
172
173 switch (ksu) {
174 case KSU_USER:
175 x_64 = status & STATUS_UX;
176 break;
177 case KSU_KERNEL:
178 x_64 = status & STATUS_KX;
179 break;
180 case KSU_SUPERVISOR:
181 x_64 = status & STATUS_SX;
182 /* FALLTHROUGH, since supervisor address spaces are not
183 really implemented yet. */
184 default:fatal("memory_mips_v2p.c: ksu=%i not yet implemented yet\n",
185 ksu);
186 exit(1);
187 }
188
189 n_tlbs = cpu->cd.mips.cpu_type.nr_of_tlb_entries;
190
191 /* Having this here suppresses a compiler warning: */
192 pageshift = 12;
193
194 /* KUSEG: 0x00000000 - 0x7fffffff if ERL = 1 and KSU = kernel: */
195 if (ksu == KSU_KERNEL && (status & STATUS_ERL) &&
196 vaddr <= 0x7fffffff) {
197 *return_paddr = vaddr & 0x7fffffff;
198 return 2;
199 }
200
201 /*
202 * XKPHYS: 0x8000000000000000 - 0xbfffffffffffffff
203 *
204 * TODO: Is the correct error generated if accessing XKPHYS from
205 * usermode?
206 *
207 * TODO: Magic on SGI machines... Cache control, NUMA, etc.:
208 * 0x9000000080000000 = disable L2 cache (?)
209 * 0x90000000a0000000 = something on IP30?
210 * 0x92.... and 0x96... = NUMA on IP27
211 */
212 if (ksu == KSU_KERNEL && (vaddr & ENTRYHI_R_MASK) == ENTRYHI_R_XKPHYS) {
213 *return_paddr = vaddr & (((uint64_t)1 << 44) - 1);
214 return 2;
215 }
216
217 /* This is needed later: */
218 vaddr_asid = cp0->reg[COP0_ENTRYHI] & ENTRYHI_ASID;
219 /* vpn2 depends on pagemask, which is not fixed on R4000 */
220 #endif
221
222 /* If 32-bit, truncate address and sign extend: */
223 if (x_64 == 0) {
224 vaddr = (int32_t) vaddr;
225 xuseg_top = 0x7fffffff;
226 /* (Actually useg for R2000/R3000) */
227 }
228
229 if (vaddr <= xuseg_top) {
230 use_tlb = 1;
231 } else {
232 if (ksu == KSU_KERNEL) {
233 /* kseg0, kseg1: */
234 if (vaddr >= (uint64_t)0xffffffff80000000ULL &&
235 vaddr <= (uint64_t)0xffffffffbfffffffULL) {
236 *return_paddr = vaddr & 0x1fffffff;
237 return 2;
238 }
239
240 /* other segments: */
241 use_tlb = 1;
242 } else {
243 use_tlb = 0;
244 }
245 }
246
247 if (use_tlb) {
248 #ifndef V2P_MMU3K
249 int odd = 0;
250 uint64_t cached_lo1 = 0;
251 #endif
252 int g_bit, v_bit, d_bit;
253 uint64_t cached_hi, cached_lo0;
254 uint64_t entry_vpn2 = 0, entry_asid, pfn;
255 int i_end;
256
257 i = cpu->cd.mips.last_written_tlb_index;
258 i_end = i == 0? n_tlbs-1 : i - 1;
259
260 /* Scan all TLB entries: */
261 for (;;) {
262 #ifdef V2P_MMU3K
263 /* R3000 or similar: */
264 cached_hi = cp0->tlbs[i].hi;
265 cached_lo0 = cp0->tlbs[i].lo0;
266
267 entry_vpn2 = cached_hi & R2K3K_ENTRYHI_VPN_MASK;
268 entry_asid = cached_hi & R2K3K_ENTRYHI_ASID_MASK;
269 g_bit = cached_lo0 & R2K3K_ENTRYLO_G;
270 v_bit = cached_lo0 & R2K3K_ENTRYLO_V;
271 d_bit = cached_lo0 & R2K3K_ENTRYLO_D;
272 #else
273 /* R4000 or similar: */
274 pmask = cp0->tlbs[i].mask & pagemask_mask;
275 cached_hi = cp0->tlbs[i].hi;
276 cached_lo0 = cp0->tlbs[i].lo0;
277 cached_lo1 = cp0->tlbs[i].lo1;
278
279 /* Optimized for minimum page size: */
280 if (pmask == 0) {
281 pageshift = pagemask_shift - 1;
282 entry_vpn2 = (cached_hi & vpn2_mask)
283 >> pagemask_shift;
284 vaddr_vpn2 = (vaddr & vpn2_mask)
285 >> pagemask_shift;
286 pmask = (1 << (pagemask_shift-1)) - 1;
287 odd = (vaddr >> (pagemask_shift-1)) & 1;
288 } else {
289 /* Non-standard page mask: */
290 switch (pmask | ((1 << pagemask_shift) - 1)) {
291 case 0x00007ff: pageshift = 10; break;
292 case 0x0001fff: pageshift = 12; break;
293 case 0x0007fff: pageshift = 14; break;
294 case 0x001ffff: pageshift = 16; break;
295 case 0x007ffff: pageshift = 18; break;
296 case 0x01fffff: pageshift = 20; break;
297 case 0x07fffff: pageshift = 22; break;
298 case 0x1ffffff: pageshift = 24; break;
299 case 0x7ffffff: pageshift = 26; break;
300 default:fatal("pmask=%08x\n", pmask);
301 exit(1);
302 }
303
304 entry_vpn2 = (cached_hi &
305 vpn2_mask) >> (pageshift + 1);
306 vaddr_vpn2 = (vaddr & vpn2_mask) >>
307 (pageshift + 1);
308 pmask = (1 << pageshift) - 1;
309 odd = (vaddr >> pageshift) & 1;
310 }
311
312 /* Assume even virtual page... */
313 v_bit = cached_lo0 & ENTRYLO_V;
314 d_bit = cached_lo0 & ENTRYLO_D;
315
316 #ifdef V2P_MMU8K
317 /*
318 * TODO: I don't really know anything about the R8000.
319 * http://futuretech.mirror.vuurwerk.net/i2sec7.html
320 * says that it has a three-way associative TLB with
321 * 384 entries, 16KB page size, and some other things.
322 *
323 * It feels like things like the valid bit (ala R4000)
324 * and dirty bit are not implemented the same on R8000.
325 *
326 * http://sgistuff.tastensuppe.de/documents/
327 * R8000_chipset.html
328 * also has some info, but no details.
329 */
330 v_bit = 1; /* Big TODO */
331 d_bit = 1;
332 #endif
333
334 entry_asid = cached_hi & ENTRYHI_ASID;
335
336 /* ... reload pfn, v_bit, d_bit if
337 it was the odd virtual page: */
338 if (odd) {
339 v_bit = cached_lo1 & ENTRYLO_V;
340 d_bit = cached_lo1 & ENTRYLO_D;
341 }
342 #ifdef V2P_MMU4100
343 g_bit = cached_lo1 & cached_lo0 & ENTRYLO_G;
344 #else
345 g_bit = cached_hi & TLB_G;
346 #endif
347
348 #endif
349
350 /* Is there a VPN and ASID match? */
351 if (entry_vpn2 == vaddr_vpn2 &&
352 (entry_asid == vaddr_asid || g_bit)) {
353 /* debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" "
354 "==> paddr %016"PRIx64" v=%i d=%i "
355 "asid=0x%02x }\n", i, (uint64_t) vaddr,
356 (uint64_t) *return_paddr, v_bit?1:0,
357 d_bit?1:0, vaddr_asid); */
358 if (v_bit) {
359 if (d_bit || (!d_bit &&
360 writeflag == MEM_READ)) {
361 uint64_t paddr;
362 /* debug("OK MAP 2!!! { w=%i "
363 "vaddr=%016"PRIx64" ==> "
364 "d=%i v=%i paddr %016"
365 PRIx64" ",
366 writeflag, (uint64_t)vaddr,
367 d_bit?1:0, v_bit?1:0,
368 (uint64_t) *return_paddr);
369 debug(", tlb entry %2i: ma"
370 "sk=%016"PRIx64" hi=%016"
371 PRIx64" lo0=%016"PRIx64
372 " lo1=%016"PRIx64"\n",
373 i, cp0->tlbs[i].mask, cp0->
374 tlbs[i].hi, cp0->tlbs[i].
375 lo0, cp0->tlbs[i].lo1);
376 */
377 #ifdef V2P_MMU3K
378 pfn = cached_lo0 &
379 R2K3K_ENTRYLO_PFN_MASK;
380 paddr = pfn | (vaddr & pmask);
381 #else
382 pfn = ((odd? cached_lo1 :
383 cached_lo0)
384 & ENTRYLO_PFN_MASK)
385 >> ENTRYLO_PFN_SHIFT;
386 paddr = (pfn << pfn_shift) |
387 (vaddr & pmask);
388 #endif
389
390 *return_paddr = paddr;
391 return d_bit? 2 : 1;
392 } else {
393 /* TLB modif. exception */
394 tlb_refill = 0;
395 exccode = EXCEPTION_MOD;
396 goto exception;
397 }
398 } else {
399 /* TLB invalid exception */
400 tlb_refill = 0;
401 goto exception;
402 }
403 }
404
405 if (i == i_end)
406 break;
407
408 /* Go to the next TLB entry: */
409 i ++;
410 if (i == n_tlbs)
411 i = 0;
412 }
413 }
414
415 /*
416 * We are here if for example userland code tried to access
417 * kernel memory, OR if there was a TLB refill.
418 */
419
420 if (!use_tlb) {
421 tlb_refill = 0;
422 if (writeflag == MEM_WRITE)
423 exccode = EXCEPTION_ADES;
424 else
425 exccode = EXCEPTION_ADEL;
426 }
427
428 exception:
429 if (no_exceptions)
430 return 0;
431
432 /* TLB Load or Store exception: */
433 if (exccode == -1) {
434 if (writeflag == MEM_WRITE)
435 exccode = EXCEPTION_TLBS;
436 else
437 exccode = EXCEPTION_TLBL;
438 }
439
440 #ifdef V2P_MMU3K
441 vaddr_asid >>= R2K3K_ENTRYHI_ASID_SHIFT;
442 vaddr_vpn2 >>= 12;
443 #endif
444
445 mips_cpu_exception(cpu, exccode, tlb_refill, vaddr,
446 0, vaddr_vpn2, vaddr_asid, x_64);
447
448 /* Return failure: */
449 return 0;
450 }
451
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