25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: memory_mips_v2p.c,v 1.5 2006/06/16 18:31:26 debug Exp $ |
* $Id: memory_mips_v2p.c,v 1.6 2006/06/24 21:47:23 debug Exp $ |
29 |
* |
* |
30 |
* Included from memory.c. |
* Included from memory.c. |
31 |
*/ |
*/ |
32 |
|
|
33 |
|
|
34 |
/* |
/* |
35 |
* translate_address(): |
* translate_v2p(): |
36 |
* |
* |
37 |
* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
38 |
* |
* |
44 |
* 2 Success, the page is read/write |
* 2 Success, the page is read/write |
45 |
*/ |
*/ |
46 |
int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr, |
int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr, |
47 |
uint64_t *return_addr, int flags) |
uint64_t *return_paddr, int flags) |
48 |
{ |
{ |
49 |
int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ; |
int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ; |
50 |
int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
195 |
* On IP27 (and probably others), addresses such as |
* On IP27 (and probably others), addresses such as |
196 |
* 0x92... and 0x96... have to do with NUMA stuff. |
* 0x92... and 0x96... have to do with NUMA stuff. |
197 |
*/ |
*/ |
198 |
*return_addr = vaddr & (((uint64_t)1 << 44) - 1); |
*return_paddr = vaddr & (((uint64_t)1 << 44) - 1); |
199 |
return 2; |
return 2; |
200 |
} |
} |
201 |
|
|
219 |
/* kseg0, kseg1: */ |
/* kseg0, kseg1: */ |
220 |
if (vaddr >= (uint64_t)0xffffffff80000000ULL && |
if (vaddr >= (uint64_t)0xffffffff80000000ULL && |
221 |
vaddr <= (uint64_t)0xffffffffbfffffffULL) { |
vaddr <= (uint64_t)0xffffffffbfffffffULL) { |
222 |
*return_addr = vaddr & 0x1fffffff; |
*return_paddr = vaddr & 0x1fffffff; |
223 |
return 2; |
return 2; |
224 |
} |
} |
225 |
|
|
335 |
/* debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" " |
/* debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" " |
336 |
"==> paddr %016"PRIx64" v=%i d=%i " |
"==> paddr %016"PRIx64" v=%i d=%i " |
337 |
"asid=0x%02x }\n", i, (uint64_t) vaddr, |
"asid=0x%02x }\n", i, (uint64_t) vaddr, |
338 |
(uint64_t) *return_addr, v_bit?1:0, |
(uint64_t) *return_paddr, v_bit?1:0, |
339 |
d_bit?1:0, vaddr_asid); */ |
d_bit?1:0, vaddr_asid); */ |
340 |
if (v_bit) { |
if (v_bit) { |
341 |
if (d_bit || (!d_bit && |
if (d_bit || (!d_bit && |
347 |
PRIx64" ", |
PRIx64" ", |
348 |
writeflag, (uint64_t)vaddr, |
writeflag, (uint64_t)vaddr, |
349 |
d_bit?1:0, v_bit?1:0, |
d_bit?1:0, v_bit?1:0, |
350 |
(uint64_t) *return_addr); |
(uint64_t) *return_paddr); |
351 |
debug(", tlb entry %2i: ma" |
debug(", tlb entry %2i: ma" |
352 |
"sk=%016"PRIx64" hi=%016" |
"sk=%016"PRIx64" hi=%016" |
353 |
PRIx64" lo0=%016"PRIx64 |
PRIx64" lo0=%016"PRIx64 |
369 |
(vaddr & pmask); |
(vaddr & pmask); |
370 |
#endif |
#endif |
371 |
|
|
372 |
*return_addr = paddr; |
*return_paddr = paddr; |
373 |
return d_bit? 2 : 1; |
return d_bit? 2 : 1; |
374 |
} else { |
} else { |
375 |
/* TLB modif. exception */ |
/* TLB modif. exception */ |