--- trunk/src/cpus/memory_mips_v2p.c	2007/10/08 16:19:23	20
+++ trunk/src/cpus/memory_mips_v2p.c	2007/10/08 16:20:10	26
@@ -25,14 +25,14 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: memory_mips_v2p.c,v 1.2 2005/11/11 13:23:16 debug Exp $
+ *  $Id: memory_mips_v2p.c,v 1.6 2006/06/24 21:47:23 debug Exp $
  *
  *  Included from memory.c.
  */
 
 
 /*
- *  translate_address():
+ *  translate_v2p():
  *
  *  Don't call this function is userland_emul is non-NULL, or cpu is NULL.
  *
@@ -44,16 +44,14 @@
  *	2  Success, the page is read/write
  */
 int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr,
-	uint64_t *return_addr, int flags)
+	uint64_t *return_paddr, int flags)
 {
 	int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ;
 	int no_exceptions = flags & FLAG_NOEXCEPTIONS;
-	int instr = flags & FLAG_INSTR;
 	int ksu, use_tlb, status, i;
 	uint64_t vaddr_vpn2=0, vaddr_asid=0;
 	int exccode, tlb_refill;
 	struct mips_coproc *cp0;
-	int bintrans_cached = cpu->machine->bintrans_enable;
 
 #ifdef V2P_MMU3K
 	const int x_64 = 0;
@@ -85,51 +83,6 @@
 #endif	/*  !V2P_MMU3K  */
 
 
-#ifdef USE_TINY_CACHE
-	/*
-	 *  Check the tiny translation cache first:
-	 *
-	 *  Only userland addresses are checked, because other addresses
-	 *  are probably better of being statically translated, or through
-	 *  the TLB.  (Note: When running with 64-bit addresses, this
-	 *  will still produce the correct result. At worst, we check the
-	 *  cache in vain, but the result should still be correct.)
-	 */
-	if (!bintrans_cached &&
-	    (vaddr & 0xc0000000ULL) != 0x80000000ULL) {
-		int i, wf = 1 + (writeflag == MEM_WRITE);
-		uint64_t vaddr_shift_12 = vaddr >> 12;
-
-		if (instr) {
-			/*  Code:  */
-			for (i=0; i<N_TRANSLATION_CACHE_INSTR; i++) {
-				if (cpu->cd.mips.translation_cache_instr[i].wf
-				    >= wf && vaddr_shift_12 == (cpu->cd.mips.
-				    translation_cache_instr[i].vaddr_pfn)) {
-					*return_addr = cpu->cd.mips.
-					    translation_cache_instr[i].paddr
-					    | (vaddr & 0xfff);
-					return cpu->cd.mips.
-					    translation_cache_instr[i].wf;
-				}
-			}
-		} else {
-			/*  Data:  */
-			for (i=0; i<N_TRANSLATION_CACHE_DATA; i++) {
-				if (cpu->cd.mips.translation_cache_data[i].wf
-				    >= wf && vaddr_shift_12 == (cpu->cd.mips.
-				    translation_cache_data[i].vaddr_pfn)) {
-					*return_addr = cpu->cd.mips.
-					    translation_cache_data[i].paddr
-					    | (vaddr & 0xfff);
-					return cpu->cd.mips.
-					    translation_cache_data[i].wf;
-				}
-			}
-		}
-	}
-#endif
-
 	exccode = -1;
 	tlb_refill = 1;
 
@@ -242,7 +195,7 @@
 		 *  On IP27 (and probably others), addresses such as
 		 *  0x92... and 0x96... have to do with NUMA stuff.
 		 */
-		*return_addr = vaddr & (((uint64_t)1 << 44) - 1);
+		*return_paddr = vaddr & (((uint64_t)1 << 44) - 1);
 		return 2;
 	}
 
@@ -266,7 +219,7 @@
 			/*  kseg0, kseg1:  */
 			if (vaddr >= (uint64_t)0xffffffff80000000ULL &&
 			    vaddr <= (uint64_t)0xffffffffbfffffffULL) {
-				*return_addr = vaddr & 0x1fffffff;
+				*return_paddr = vaddr & 0x1fffffff;
 				return 2;
 			}
 
@@ -280,7 +233,8 @@
 
 	if (use_tlb) {
 #ifndef V2P_MMU3K
-		int odd = 0, cached_lo1 = 0;
+		int odd = 0;
+		uint64_t cached_lo1 = 0;
 #endif
 		int g_bit, v_bit, d_bit;
 		uint64_t cached_hi, cached_lo0;
@@ -378,24 +332,26 @@
 			/*  Is there a VPN and ASID match?  */
 			if (entry_vpn2 == vaddr_vpn2 &&
 			    (entry_asid == vaddr_asid || g_bit)) {
-				/*  debug("OK MAP 1, i=%i { vaddr=%016llx "
-				    "==> paddr %016llx v=%i d=%i "
-				    "asid=0x%02x }\n", i, (long long)vaddr,
-				    (long long) *return_addr, v_bit?1:0,
+				/*  debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" "
+				    "==> paddr %016"PRIx64" v=%i d=%i "
+				    "asid=0x%02x }\n", i, (uint64_t) vaddr,
+				    (uint64_t) *return_paddr, v_bit?1:0,
 				    d_bit?1:0, vaddr_asid);  */
 				if (v_bit) {
 					if (d_bit || (!d_bit &&
 					    writeflag == MEM_READ)) {
 						uint64_t paddr;
 						/*  debug("OK MAP 2!!! { w=%i "
-						    "vaddr=%016llx ==> d=%i v="
-						    "%i paddr %016llx ",
-						    writeflag, (long long)vaddr,
+						    "vaddr=%016"PRIx64" ==> "
+						    "d=%i v=%i paddr %016"
+						    PRIx64" ",
+						    writeflag, (uint64_t)vaddr,
 						    d_bit?1:0, v_bit?1:0,
-						    (long long) *return_addr);
+						    (uint64_t) *return_paddr);
 						    debug(", tlb entry %2i: ma"
-						    "sk=%016llx hi=%016llx lo0"
-						    "=%016llx lo1=%016llx\n",
+						    "sk=%016"PRIx64" hi=%016"
+						    PRIx64" lo0=%016"PRIx64
+						    " lo1=%016"PRIx64"\n",
 						    i, cp0->tlbs[i].mask, cp0->
 						    tlbs[i].hi, cp0->tlbs[i].
 						    lo0, cp0->tlbs[i].lo1);
@@ -413,19 +369,7 @@
 						    (vaddr & pmask);
 #endif
 
-						/*
-						 *  Enter into the tiny trans-
-						 *  lation cache (if enabled)
-						 *  and return:
-						 */
-						if (!bintrans_cached)
-							insert_into_tiny_cache(
-							    cpu, instr, d_bit?
-							    MEM_WRITE :
-							    MEM_READ,
-							    vaddr, paddr);
-
-						*return_addr = paddr;
+						*return_paddr = paddr;
 						return d_bit? 2 : 1;
 					} else {
 						/*  TLB modif. exception  */