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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: memory_mips_v2p.c,v 1.5 2006/06/16 18:31:26 debug Exp $ |
* $Id: memory_mips_v2p.c,v 1.7 2006/07/16 13:32:26 debug Exp $ |
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* |
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* Included from memory.c. |
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*/ |
*/ |
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/* |
/* |
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* translate_address(): |
* translate_v2p(): |
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* |
* |
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* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
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* |
* |
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* 2 Success, the page is read/write |
* 2 Success, the page is read/write |
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*/ |
*/ |
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int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr, |
int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags) |
uint64_t *return_paddr, int flags) |
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{ |
{ |
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int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ; |
int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ; |
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int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
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* On IP27 (and probably others), addresses such as |
* On IP27 (and probably others), addresses such as |
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* 0x92... and 0x96... have to do with NUMA stuff. |
* 0x92... and 0x96... have to do with NUMA stuff. |
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*/ |
*/ |
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*return_addr = vaddr & (((uint64_t)1 << 44) - 1); |
*return_paddr = vaddr & (((uint64_t)1 << 44) - 1); |
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return 2; |
return 2; |
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} |
} |
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/* kseg0, kseg1: */ |
/* kseg0, kseg1: */ |
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if (vaddr >= (uint64_t)0xffffffff80000000ULL && |
if (vaddr >= (uint64_t)0xffffffff80000000ULL && |
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vaddr <= (uint64_t)0xffffffffbfffffffULL) { |
vaddr <= (uint64_t)0xffffffffbfffffffULL) { |
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*return_addr = vaddr & 0x1fffffff; |
*return_paddr = vaddr & 0x1fffffff; |
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return 2; |
return 2; |
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} |
} |
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/* debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" " |
/* debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" " |
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"==> paddr %016"PRIx64" v=%i d=%i " |
"==> paddr %016"PRIx64" v=%i d=%i " |
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"asid=0x%02x }\n", i, (uint64_t) vaddr, |
"asid=0x%02x }\n", i, (uint64_t) vaddr, |
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(uint64_t) *return_addr, v_bit?1:0, |
(uint64_t) *return_paddr, v_bit?1:0, |
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d_bit?1:0, vaddr_asid); */ |
d_bit?1:0, vaddr_asid); */ |
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if (v_bit) { |
if (v_bit) { |
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if (d_bit || (!d_bit && |
if (d_bit || (!d_bit && |
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PRIx64" ", |
PRIx64" ", |
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writeflag, (uint64_t)vaddr, |
writeflag, (uint64_t)vaddr, |
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d_bit?1:0, v_bit?1:0, |
d_bit?1:0, v_bit?1:0, |
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(uint64_t) *return_addr); |
(uint64_t) *return_paddr); |
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debug(", tlb entry %2i: ma" |
debug(", tlb entry %2i: ma" |
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"sk=%016"PRIx64" hi=%016" |
"sk=%016"PRIx64" hi=%016" |
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PRIx64" lo0=%016"PRIx64 |
PRIx64" lo0=%016"PRIx64 |
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(vaddr & pmask); |
(vaddr & pmask); |
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#endif |
#endif |
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*return_addr = paddr; |
*return_paddr = paddr; |
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return d_bit? 2 : 1; |
return d_bit? 2 : 1; |
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} else { |
} else { |
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/* TLB modif. exception */ |
/* TLB modif. exception */ |