25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: memory_mips.c,v 1.2 2005/11/30 16:23:09 debug Exp $ |
* $Id: memory_mips.c,v 1.9 2006/07/14 16:33:28 debug Exp $ |
29 |
* |
* |
30 |
* MIPS-specific memory routines. Included from cpu_mips.c. |
* MIPS-specific memory routines. Included from cpu_mips.c. |
31 |
|
* |
32 |
|
* NOTE: The cache emulation code (ifdef ENABLE_CACHE_EMULATION) is old |
33 |
|
* and doesn't work with dyntrans. TODO: rewrite this. |
34 |
*/ |
*/ |
35 |
|
|
36 |
#include <sys/types.h> |
#include <sys/types.h> |
38 |
|
|
39 |
|
|
40 |
/* |
/* |
|
* insert_into_tiny_cache(): |
|
|
* |
|
|
* If the tiny cache is enabled (USE_TINY_CACHE), then this routine inserts |
|
|
* a vaddr to paddr translation first in the instruction (or data) tiny |
|
|
* translation cache. |
|
|
*/ |
|
|
static void insert_into_tiny_cache(struct cpu *cpu, int instr, int writeflag, |
|
|
uint64_t vaddr, uint64_t paddr) |
|
|
{ |
|
|
#ifdef USE_TINY_CACHE |
|
|
int wf = 1 + (writeflag == MEM_WRITE); |
|
|
|
|
|
if (cpu->machine->bintrans_enable) |
|
|
return; |
|
|
|
|
|
paddr &= ~0xfff; |
|
|
vaddr >>= 12; |
|
|
|
|
|
if (instr) { |
|
|
/* Code: */ |
|
|
memmove(&cpu->cd.mips.translation_cache_instr[1], |
|
|
&cpu->cd.mips.translation_cache_instr[0], |
|
|
sizeof(struct translation_cache_entry) * |
|
|
(N_TRANSLATION_CACHE_INSTR - 1)); |
|
|
|
|
|
cpu->cd.mips.translation_cache_instr[0].wf = wf; |
|
|
cpu->cd.mips.translation_cache_instr[0].vaddr_pfn = vaddr; |
|
|
cpu->cd.mips.translation_cache_instr[0].paddr = paddr; |
|
|
} else { |
|
|
/* Data: */ |
|
|
memmove(&cpu->cd.mips.translation_cache_data[1], |
|
|
&cpu->cd.mips.translation_cache_data[0], |
|
|
sizeof(struct translation_cache_entry) * |
|
|
(N_TRANSLATION_CACHE_DATA - 1)); |
|
|
|
|
|
cpu->cd.mips.translation_cache_data[0].wf = wf; |
|
|
cpu->cd.mips.translation_cache_data[0].vaddr_pfn = vaddr; |
|
|
cpu->cd.mips.translation_cache_data[0].paddr = paddr; |
|
|
} |
|
|
#endif |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
41 |
* memory_cache_R3000(): |
* memory_cache_R3000(): |
42 |
* |
* |
43 |
* R2000/R3000 specific cache handling. |
* R2000/R3000 specific cache handling. |
54 |
uint32_t tag_mask; |
uint32_t tag_mask; |
55 |
unsigned char *memblock; |
unsigned char *memblock; |
56 |
struct memory *mem = cpu->mem; |
struct memory *mem = cpu->mem; |
|
int offset; |
|
57 |
#endif |
#endif |
58 |
unsigned int i; |
unsigned int i; |
59 |
int cache_isolated = 0, addr, hit, which_cache = cache; |
int cache_isolated = 0, addr, hit, which_cache = cache; |
76 |
hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) && |
hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) && |
77 |
(rp[cache_line].tag_paddr == (paddr & tag_mask)); |
(rp[cache_line].tag_paddr == (paddr & tag_mask)); |
78 |
|
|
|
#ifdef ENABLE_INSTRUCTION_DELAYS |
|
|
if (!hit) |
|
|
cpu->cd.mips.instruction_delay += |
|
|
cpu->cd.mips.cpu_type.instrs_per_cycle |
|
|
* cpu->cd.mips.cache_miss_penalty[which_cache]; |
|
|
#endif |
|
|
|
|
79 |
/* |
/* |
80 |
* The cache miss bit is only set on cache reads, and only to the |
* The cache miss bit is only set on cache reads, and only to the |
81 |
* data cache. (?) |
* data cache. (?) |
126 |
old_cached_paddr); |
old_cached_paddr); |
127 |
*/ |
*/ |
128 |
memblock = memory_paddr_to_hostaddr( |
memblock = memory_paddr_to_hostaddr( |
129 |
mem, old_cached_paddr, MEM_WRITE); |
mem, old_cached_paddr & ~cpu->cd.mips. |
130 |
offset = old_cached_paddr |
cache_mask[which_cache], MEM_WRITE); |
|
& ((1 << BITS_PER_MEMBLOCK) - 1) |
|
|
& ~cpu->cd.mips.cache_mask[which_cache]; |
|
131 |
|
|
132 |
src = cpu->cd.mips.cache[which_cache]; |
src = cpu->cd.mips.cache[which_cache]; |
133 |
dst = memblock + (offset & |
dst = memblock; |
|
~cpu->cd.mips.cache_mask[which_cache]); |
|
134 |
|
|
135 |
src += cache_line * |
src += cache_line * |
136 |
cpu->cd.mips.cache_linesize[which_cache]; |
cpu->cd.mips.cache_linesize[which_cache]; |
143 |
memcpy(dst, src, |
memcpy(dst, src, |
144 |
cpu->cd.mips.cache_linesize[which_cache]); |
cpu->cd.mips.cache_linesize[which_cache]); |
145 |
} |
} |
|
/* offset is the offset within |
|
|
* the memblock: |
|
|
* printf("read: offset = 0x%x\n", offset); |
|
|
*/ |
|
146 |
} |
} |
147 |
|
|
148 |
/* Copy from main memory into the cache: */ |
/* Copy from main memory into the cache: */ |
149 |
memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
memblock = memory_paddr_to_hostaddr(mem, paddr |
150 |
offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1) |
& ~cpu->cd.mips.cache_mask[which_cache], writeflag); |
|
& ~cpu->cd.mips.cache_mask[which_cache]; |
|
|
/* offset is offset within the memblock: |
|
|
* printf("write: offset = 0x%x\n", offset); |
|
|
*/ |
|
151 |
|
|
152 |
/* fatal(" FETCHING new paddr=0%08x\n", paddr); |
/* fatal(" FETCHING new paddr=0%08x\n", paddr); |
153 |
*/ |
*/ |
158 |
memset(dst, 0, |
memset(dst, 0, |
159 |
cpu->cd.mips.cache_linesize[which_cache]); |
cpu->cd.mips.cache_linesize[which_cache]); |
160 |
} else { |
} else { |
161 |
src = memblock + (offset & |
src = memblock; |
|
~cpu->cd.mips.cache_mask[which_cache]); |
|
162 |
|
|
163 |
src += cache_line * |
src += cache_line * |
164 |
cpu->cd.mips.cache_linesize[which_cache]; |
cpu->cd.mips.cache_linesize[which_cache]; |
191 |
} |
} |
192 |
} |
} |
193 |
|
|
|
/* Run instructions from the right host page: */ |
|
|
if (cache == CACHE_INSTRUCTION) { |
|
|
memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
|
|
if (memblock != NULL) { |
|
|
cpu->cd.mips.pc_last_host_4k_page = memblock + |
|
|
(paddr & ((1 << BITS_PER_MEMBLOCK) - 1) & ~0xfff); |
|
|
} |
|
|
} |
|
|
|
|
194 |
/* Write-through! (Write to main memory as well.) */ |
/* Write-through! (Write to main memory as well.) */ |
195 |
if (writeflag == MEM_READ || cache_isolated) |
if (writeflag == MEM_READ || cache_isolated) |
196 |
return 1; |
return 1; |
213 |
& ~cpu->cd.mips.cache_mask[which_cache]) |
& ~cpu->cd.mips.cache_mask[which_cache]) |
214 |
== (paddr & ~(cpu->cd.mips.cache_mask[which_cache])); |
== (paddr & ~(cpu->cd.mips.cache_mask[which_cache])); |
215 |
|
|
|
#ifdef ENABLE_INSTRUCTION_DELAYS |
|
|
if (!hit) |
|
|
cpu->cd.mips.instruction_delay += |
|
|
cpu->cd.mips.cpu_type.instrs_per_cycle |
|
|
* cpu->cd.mips.cache_miss_penalty[which_cache]; |
|
|
#endif |
|
|
|
|
216 |
/* |
/* |
217 |
* The cache miss bit is only set on cache reads, and only to the |
* The cache miss bit is only set on cache reads, and only to the |
218 |
* data cache. (?) |
* data cache. (?) |
237 |
|
|
238 |
/* Data cache isolated? Then don't access main memory: */ |
/* Data cache isolated? Then don't access main memory: */ |
239 |
if (cache_isolated) { |
if (cache_isolated) { |
240 |
/* debug("ISOLATED write=%i cache=%i vaddr=%016llx " |
/* debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" " |
241 |
"paddr=%016llx => addr in cache = 0x%lx\n", |
"paddr=%016"PRIx64" => addr in cache = 0x%lx\n", |
242 |
writeflag, cache, (long long)vaddr, |
writeflag, cache, (uint64_t) vaddr, |
243 |
(long long)paddr, addr); */ |
(uint64_t) paddr, addr); */ |
244 |
|
|
245 |
if (writeflag==MEM_READ) { |
if (writeflag==MEM_READ) { |
246 |
for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
264 |
} |
} |
265 |
|
|
266 |
|
|
267 |
#define TRANSLATE_ADDRESS translate_address_mmu3k |
#define TRANSLATE_ADDRESS translate_v2p_mmu3k |
268 |
#define V2P_MMU3K |
#define V2P_MMU3K |
269 |
#include "memory_mips_v2p.c" |
#include "memory_mips_v2p.c" |
270 |
#undef TRANSLATE_ADDRESS |
#undef TRANSLATE_ADDRESS |
271 |
#undef V2P_MMU3K |
#undef V2P_MMU3K |
272 |
|
|
273 |
#define TRANSLATE_ADDRESS translate_address_mmu8k |
#define TRANSLATE_ADDRESS translate_v2p_mmu8k |
274 |
#define V2P_MMU8K |
#define V2P_MMU8K |
275 |
#include "memory_mips_v2p.c" |
#include "memory_mips_v2p.c" |
276 |
#undef TRANSLATE_ADDRESS |
#undef TRANSLATE_ADDRESS |
277 |
#undef V2P_MMU8K |
#undef V2P_MMU8K |
278 |
|
|
279 |
#define TRANSLATE_ADDRESS translate_address_mmu10k |
#define TRANSLATE_ADDRESS translate_v2p_mmu10k |
280 |
#define V2P_MMU10K |
#define V2P_MMU10K |
281 |
#include "memory_mips_v2p.c" |
#include "memory_mips_v2p.c" |
282 |
#undef TRANSLATE_ADDRESS |
#undef TRANSLATE_ADDRESS |
283 |
#undef V2P_MMU10K |
#undef V2P_MMU10K |
284 |
|
|
285 |
/* Almost generic :-) */ |
/* Almost generic :-) */ |
286 |
#define TRANSLATE_ADDRESS translate_address_mmu4100 |
#define TRANSLATE_ADDRESS translate_v2p_mmu4100 |
287 |
#define V2P_MMU4100 |
#define V2P_MMU4100 |
288 |
#include "memory_mips_v2p.c" |
#include "memory_mips_v2p.c" |
289 |
#undef TRANSLATE_ADDRESS |
#undef TRANSLATE_ADDRESS |
290 |
#undef V2P_MMU4100 |
#undef V2P_MMU4100 |
291 |
|
|
292 |
#define TRANSLATE_ADDRESS translate_address_generic |
#define TRANSLATE_ADDRESS translate_v2p_generic |
293 |
#include "memory_mips_v2p.c" |
#include "memory_mips_v2p.c" |
294 |
|
|
295 |
|
|
|
#ifndef EXPERIMENTAL_NEWMIPS |
|
|
|
|
|
#define MEMORY_RW mips_memory_rw |
|
|
#define MEM_MIPS |
|
|
#include "../memory_rw.c" |
|
|
#undef MEM_MIPS |
|
|
#undef MEMORY_RW |
|
|
|
|
|
#endif |
|