/[gxemul]/trunk/src/cpus/memory_mips.c
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Diff of /trunk/src/cpus/memory_mips.c

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revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: memory_mips.c,v 1.2 2005/11/30 16:23:09 debug Exp $   *  $Id: memory_mips.c,v 1.7 2006/06/22 11:43:03 debug Exp $
29   *   *
30   *  MIPS-specific memory routines. Included from cpu_mips.c.   *  MIPS-specific memory routines. Included from cpu_mips.c.
31     *
32     *  NOTE: The cache emulation code (ifdef ENABLE_CACHE_EMULATION) is old
33     *        and doesn't work with dyntrans. TODO: rewrite this.
34   */   */
35    
36  #include <sys/types.h>  #include <sys/types.h>
# Line 35  Line 38 
38    
39    
40  /*  /*
  *  insert_into_tiny_cache():  
  *  
  *  If the tiny cache is enabled (USE_TINY_CACHE), then this routine inserts  
  *  a vaddr to paddr translation first in the instruction (or data) tiny  
  *  translation cache.  
  */  
 static void insert_into_tiny_cache(struct cpu *cpu, int instr, int writeflag,  
         uint64_t vaddr, uint64_t paddr)  
 {  
 #ifdef USE_TINY_CACHE  
         int wf = 1 + (writeflag == MEM_WRITE);  
   
         if (cpu->machine->bintrans_enable)  
                 return;  
   
         paddr &= ~0xfff;  
         vaddr >>= 12;  
   
         if (instr) {  
                 /*  Code:  */  
                 memmove(&cpu->cd.mips.translation_cache_instr[1],  
                     &cpu->cd.mips.translation_cache_instr[0],  
                     sizeof(struct translation_cache_entry) *  
                     (N_TRANSLATION_CACHE_INSTR - 1));  
   
                 cpu->cd.mips.translation_cache_instr[0].wf = wf;  
                 cpu->cd.mips.translation_cache_instr[0].vaddr_pfn = vaddr;  
                 cpu->cd.mips.translation_cache_instr[0].paddr = paddr;  
         } else {  
                 /*  Data:  */  
                 memmove(&cpu->cd.mips.translation_cache_data[1],  
                     &cpu->cd.mips.translation_cache_data[0],  
                     sizeof(struct translation_cache_entry) *  
                     (N_TRANSLATION_CACHE_DATA - 1));  
   
                 cpu->cd.mips.translation_cache_data[0].wf = wf;  
                 cpu->cd.mips.translation_cache_data[0].vaddr_pfn = vaddr;  
                 cpu->cd.mips.translation_cache_data[0].paddr = paddr;  
         }  
 #endif  
 }  
   
   
 /*  
41   *  memory_cache_R3000():   *  memory_cache_R3000():
42   *   *
43   *  R2000/R3000 specific cache handling.   *  R2000/R3000 specific cache handling.
# Line 118  int memory_cache_R3000(struct cpu *cpu, Line 77  int memory_cache_R3000(struct cpu *cpu,
77          hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) &&          hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) &&
78              (rp[cache_line].tag_paddr == (paddr & tag_mask));              (rp[cache_line].tag_paddr == (paddr & tag_mask));
79    
 #ifdef ENABLE_INSTRUCTION_DELAYS  
         if (!hit)  
                 cpu->cd.mips.instruction_delay +=  
                     cpu->cd.mips.cpu_type.instrs_per_cycle  
                     * cpu->cd.mips.cache_miss_penalty[which_cache];  
 #endif  
   
80          /*          /*
81           *  The cache miss bit is only set on cache reads, and only to the           *  The cache miss bit is only set on cache reads, and only to the
82           *  data cache. (?)           *  data cache. (?)
# Line 252  int memory_cache_R3000(struct cpu *cpu, Line 204  int memory_cache_R3000(struct cpu *cpu,
204                  }                  }
205          }          }
206    
         /*  Run instructions from the right host page:  */  
         if (cache == CACHE_INSTRUCTION) {  
                 memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag);  
                 if (memblock != NULL) {  
                         cpu->cd.mips.pc_last_host_4k_page = memblock +  
                             (paddr & ((1 << BITS_PER_MEMBLOCK) - 1) & ~0xfff);  
                 }  
         }  
   
207          /*  Write-through! (Write to main memory as well.)  */          /*  Write-through! (Write to main memory as well.)  */
208          if (writeflag == MEM_READ || cache_isolated)          if (writeflag == MEM_READ || cache_isolated)
209                  return 1;                  return 1;
# Line 283  int memory_cache_R3000(struct cpu *cpu, Line 226  int memory_cache_R3000(struct cpu *cpu,
226                  & ~cpu->cd.mips.cache_mask[which_cache])                  & ~cpu->cd.mips.cache_mask[which_cache])
227              == (paddr & ~(cpu->cd.mips.cache_mask[which_cache]));              == (paddr & ~(cpu->cd.mips.cache_mask[which_cache]));
228    
 #ifdef ENABLE_INSTRUCTION_DELAYS  
         if (!hit)  
                 cpu->cd.mips.instruction_delay +=  
                     cpu->cd.mips.cpu_type.instrs_per_cycle  
                     * cpu->cd.mips.cache_miss_penalty[which_cache];  
 #endif  
   
229          /*          /*
230           *  The cache miss bit is only set on cache reads, and only to the           *  The cache miss bit is only set on cache reads, and only to the
231           *  data cache. (?)           *  data cache. (?)
# Line 314  int memory_cache_R3000(struct cpu *cpu, Line 250  int memory_cache_R3000(struct cpu *cpu,
250    
251          /*  Data cache isolated?  Then don't access main memory:  */          /*  Data cache isolated?  Then don't access main memory:  */
252          if (cache_isolated) {          if (cache_isolated) {
253                  /*  debug("ISOLATED write=%i cache=%i vaddr=%016llx "                  /*  debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" "
254                      "paddr=%016llx => addr in cache = 0x%lx\n",                      "paddr=%016"PRIx64" => addr in cache = 0x%lx\n",
255                      writeflag, cache, (long long)vaddr,                      writeflag, cache, (uint64_t) vaddr,
256                      (long long)paddr, addr);  */                      (uint64_t) paddr, addr);  */
257    
258                  if (writeflag==MEM_READ) {                  if (writeflag==MEM_READ) {
259                          for (i=0; i<len; i++)                          for (i=0; i<len; i++)
# Line 370  int memory_cache_R3000(struct cpu *cpu, Line 306  int memory_cache_R3000(struct cpu *cpu,
306  #include "memory_mips_v2p.c"  #include "memory_mips_v2p.c"
307    
308    
 #ifndef EXPERIMENTAL_NEWMIPS  
   
 #define MEMORY_RW       mips_memory_rw  
 #define MEM_MIPS  
 #include "../memory_rw.c"  
 #undef MEM_MIPS  
 #undef MEMORY_RW  
   
 #endif  
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