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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: memory_mips.c,v 1.9 2006/07/14 16:33:28 debug Exp $ |
* $Id: memory_mips.c,v 1.10 2006/09/01 16:52:58 debug Exp $ |
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* |
* |
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* MIPS-specific memory routines. Included from cpu_mips.c. |
* MIPS-specific memory routines. Included from cpu_mips.c. |
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* |
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* NOTE: The cache emulation code (ifdef ENABLE_CACHE_EMULATION) is old |
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* and doesn't work with dyntrans. TODO: rewrite this. |
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*/ |
*/ |
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#include <sys/types.h> |
#include <sys/types.h> |
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int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, |
int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, |
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int writeflag, size_t len, unsigned char *data) |
int writeflag, size_t len, unsigned char *data) |
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{ |
{ |
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#ifdef ENABLE_CACHE_EMULATION |
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struct r3000_cache_line *rp; |
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int cache_line; |
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uint32_t tag_mask; |
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unsigned char *memblock; |
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struct memory *mem = cpu->mem; |
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#endif |
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unsigned int i; |
unsigned int i; |
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int cache_isolated = 0, addr, hit, which_cache = cache; |
int cache_isolated = 0, addr, hit, which_cache = cache; |
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return 0; |
return 0; |
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#ifdef ENABLE_CACHE_EMULATION |
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if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_SWAP_CACHES) |
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which_cache ^= 1; |
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tag_mask = 0xffffffff & ~cpu->cd.mips.cache_mask[which_cache]; |
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cache_line = (paddr & cpu->cd.mips.cache_mask[which_cache]) |
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/ cpu->cd.mips.cache_linesize[which_cache]; |
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rp = (struct r3000_cache_line *) cpu->cd.mips.cache_tags[which_cache]; |
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/* Is this a cache hit or miss? */ |
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hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) && |
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(rp[cache_line].tag_paddr == (paddr & tag_mask)); |
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/* |
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* The cache miss bit is only set on cache reads, and only to the |
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* data cache. (?) |
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* |
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* (TODO: is this correct? I don't remember where I got this from.) |
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*/ |
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if (cache == CACHE_DATA && writeflag==MEM_READ) { |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~MIPS1_CACHE_MISS; |
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if (!hit) |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= |
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MIPS1_CACHE_MISS; |
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} |
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/* |
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* Is the Data cache isolated? Then don't access main memory: |
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*/ |
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if (cache == CACHE_DATA && |
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cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) |
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cache_isolated = 1; |
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addr = paddr & cpu->cd.mips.cache_mask[which_cache]; |
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/* |
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* If there was a miss and the cache is not isolated, then flush |
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* the old cacheline back to main memory, and read in the new |
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* cacheline. |
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* |
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* Then access the cache. |
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*/ |
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/* |
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fatal("L1 CACHE isolated=%i hit=%i write=%i cache=%i cacheline=%i" |
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" paddr=%08x => addr in" |
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" cache = 0x%lx\n", cache_isolated, hit, writeflag, |
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which_cache, cache_line, (int)paddr, |
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addr); |
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*/ |
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if (!hit && !cache_isolated) { |
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unsigned char *dst, *src; |
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uint64_t old_cached_paddr = rp[cache_line].tag_paddr |
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+ cache_line * cpu->cd.mips.cache_linesize[which_cache]; |
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/* Flush the old cacheline to main memory: */ |
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if ((rp[cache_line].tag_valid & R3000_TAG_VALID) && |
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(rp[cache_line].tag_valid & R3000_TAG_DIRTY)) { |
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/* fatal(" FLUSHING old tag=0%08x " |
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"old_cached_paddr=0x%08x\n", |
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rp[cache_line].tag_paddr, |
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old_cached_paddr); |
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*/ |
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memblock = memory_paddr_to_hostaddr( |
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mem, old_cached_paddr & ~cpu->cd.mips. |
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cache_mask[which_cache], MEM_WRITE); |
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src = cpu->cd.mips.cache[which_cache]; |
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dst = memblock; |
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src += cache_line * |
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cpu->cd.mips.cache_linesize[which_cache]; |
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dst += cache_line * |
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cpu->cd.mips.cache_linesize[which_cache]; |
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if (memblock == NULL) { |
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fatal("BUG in memory.c! Hm.\n"); |
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} else { |
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memcpy(dst, src, |
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cpu->cd.mips.cache_linesize[which_cache]); |
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} |
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} |
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/* Copy from main memory into the cache: */ |
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memblock = memory_paddr_to_hostaddr(mem, paddr |
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& ~cpu->cd.mips.cache_mask[which_cache], writeflag); |
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/* fatal(" FETCHING new paddr=0%08x\n", paddr); |
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*/ |
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dst = cpu->cd.mips.cache[which_cache]; |
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if (memblock == NULL) { |
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if (writeflag == MEM_READ) |
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memset(dst, 0, |
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cpu->cd.mips.cache_linesize[which_cache]); |
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} else { |
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src = memblock; |
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src += cache_line * |
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cpu->cd.mips.cache_linesize[which_cache]; |
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dst += cache_line * |
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cpu->cd.mips.cache_linesize[which_cache]; |
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memcpy(dst, src, |
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cpu->cd.mips.cache_linesize[which_cache]); |
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} |
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rp[cache_line].tag_paddr = paddr & tag_mask; |
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rp[cache_line].tag_valid = R3000_TAG_VALID; |
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} |
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if (cache_isolated && writeflag == MEM_WRITE) { |
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rp[cache_line].tag_valid = 0; |
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} |
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if (writeflag==MEM_READ) { |
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for (i=0; i<len; i++) |
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data[i] = cpu->cd.mips.cache[which_cache][(addr+i) & |
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cpu->cd.mips.cache_mask[which_cache]]; |
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} else { |
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for (i=0; i<len; i++) { |
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if (cpu->cd.mips.cache[which_cache][(addr+i) & |
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cpu->cd.mips.cache_mask[which_cache]] != data[i]) { |
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rp[cache_line].tag_valid |= R3000_TAG_DIRTY; |
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} |
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cpu->cd.mips.cache[which_cache][(addr+i) & |
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cpu->cd.mips.cache_mask[which_cache]] = data[i]; |
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} |
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} |
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/* Write-through! (Write to main memory as well.) */ |
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if (writeflag == MEM_READ || cache_isolated) |
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return 1; |
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#else |
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/* |
/* |
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* R2000/R3000 without correct cache emulation: |
* R2000/R3000 without correct cache emulation: |
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* |
* |
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/* No! Not when not emulating caches fully. (TODO?) */ |
/* No! Not when not emulating caches fully. (TODO?) */ |
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cpu->cd.mips.cache_last_paddr[cache] = paddr; |
cpu->cd.mips.cache_last_paddr[cache] = paddr; |
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} |
} |
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#endif |
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return 0; |
return 0; |
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} |
} |