--- trunk/src/cpus/memory_mips.c 2007/10/08 16:19:37 22 +++ trunk/src/cpus/memory_mips.c 2007/10/08 16:20:26 28 @@ -25,9 +25,12 @@ * SUCH DAMAGE. * * - * $Id: memory_mips.c,v 1.2 2005/11/30 16:23:09 debug Exp $ + * $Id: memory_mips.c,v 1.9 2006/07/14 16:33:28 debug Exp $ * * MIPS-specific memory routines. Included from cpu_mips.c. + * + * NOTE: The cache emulation code (ifdef ENABLE_CACHE_EMULATION) is old + * and doesn't work with dyntrans. TODO: rewrite this. */ #include @@ -35,50 +38,6 @@ /* - * insert_into_tiny_cache(): - * - * If the tiny cache is enabled (USE_TINY_CACHE), then this routine inserts - * a vaddr to paddr translation first in the instruction (or data) tiny - * translation cache. - */ -static void insert_into_tiny_cache(struct cpu *cpu, int instr, int writeflag, - uint64_t vaddr, uint64_t paddr) -{ -#ifdef USE_TINY_CACHE - int wf = 1 + (writeflag == MEM_WRITE); - - if (cpu->machine->bintrans_enable) - return; - - paddr &= ~0xfff; - vaddr >>= 12; - - if (instr) { - /* Code: */ - memmove(&cpu->cd.mips.translation_cache_instr[1], - &cpu->cd.mips.translation_cache_instr[0], - sizeof(struct translation_cache_entry) * - (N_TRANSLATION_CACHE_INSTR - 1)); - - cpu->cd.mips.translation_cache_instr[0].wf = wf; - cpu->cd.mips.translation_cache_instr[0].vaddr_pfn = vaddr; - cpu->cd.mips.translation_cache_instr[0].paddr = paddr; - } else { - /* Data: */ - memmove(&cpu->cd.mips.translation_cache_data[1], - &cpu->cd.mips.translation_cache_data[0], - sizeof(struct translation_cache_entry) * - (N_TRANSLATION_CACHE_DATA - 1)); - - cpu->cd.mips.translation_cache_data[0].wf = wf; - cpu->cd.mips.translation_cache_data[0].vaddr_pfn = vaddr; - cpu->cd.mips.translation_cache_data[0].paddr = paddr; - } -#endif -} - - -/* * memory_cache_R3000(): * * R2000/R3000 specific cache handling. @@ -95,7 +54,6 @@ uint32_t tag_mask; unsigned char *memblock; struct memory *mem = cpu->mem; - int offset; #endif unsigned int i; int cache_isolated = 0, addr, hit, which_cache = cache; @@ -118,13 +76,6 @@ hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) && (rp[cache_line].tag_paddr == (paddr & tag_mask)); -#ifdef ENABLE_INSTRUCTION_DELAYS - if (!hit) - cpu->cd.mips.instruction_delay += - cpu->cd.mips.cpu_type.instrs_per_cycle - * cpu->cd.mips.cache_miss_penalty[which_cache]; -#endif - /* * The cache miss bit is only set on cache reads, and only to the * data cache. (?) @@ -175,14 +126,11 @@ old_cached_paddr); */ memblock = memory_paddr_to_hostaddr( - mem, old_cached_paddr, MEM_WRITE); - offset = old_cached_paddr - & ((1 << BITS_PER_MEMBLOCK) - 1) - & ~cpu->cd.mips.cache_mask[which_cache]; + mem, old_cached_paddr & ~cpu->cd.mips. + cache_mask[which_cache], MEM_WRITE); src = cpu->cd.mips.cache[which_cache]; - dst = memblock + (offset & - ~cpu->cd.mips.cache_mask[which_cache]); + dst = memblock; src += cache_line * cpu->cd.mips.cache_linesize[which_cache]; @@ -195,19 +143,11 @@ memcpy(dst, src, cpu->cd.mips.cache_linesize[which_cache]); } - /* offset is the offset within - * the memblock: - * printf("read: offset = 0x%x\n", offset); - */ } /* Copy from main memory into the cache: */ - memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); - offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1) - & ~cpu->cd.mips.cache_mask[which_cache]; - /* offset is offset within the memblock: - * printf("write: offset = 0x%x\n", offset); - */ + memblock = memory_paddr_to_hostaddr(mem, paddr + & ~cpu->cd.mips.cache_mask[which_cache], writeflag); /* fatal(" FETCHING new paddr=0%08x\n", paddr); */ @@ -218,8 +158,7 @@ memset(dst, 0, cpu->cd.mips.cache_linesize[which_cache]); } else { - src = memblock + (offset & - ~cpu->cd.mips.cache_mask[which_cache]); + src = memblock; src += cache_line * cpu->cd.mips.cache_linesize[which_cache]; @@ -252,15 +191,6 @@ } } - /* Run instructions from the right host page: */ - if (cache == CACHE_INSTRUCTION) { - memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); - if (memblock != NULL) { - cpu->cd.mips.pc_last_host_4k_page = memblock + - (paddr & ((1 << BITS_PER_MEMBLOCK) - 1) & ~0xfff); - } - } - /* Write-through! (Write to main memory as well.) */ if (writeflag == MEM_READ || cache_isolated) return 1; @@ -283,13 +213,6 @@ & ~cpu->cd.mips.cache_mask[which_cache]) == (paddr & ~(cpu->cd.mips.cache_mask[which_cache])); -#ifdef ENABLE_INSTRUCTION_DELAYS - if (!hit) - cpu->cd.mips.instruction_delay += - cpu->cd.mips.cpu_type.instrs_per_cycle - * cpu->cd.mips.cache_miss_penalty[which_cache]; -#endif - /* * The cache miss bit is only set on cache reads, and only to the * data cache. (?) @@ -314,10 +237,10 @@ /* Data cache isolated? Then don't access main memory: */ if (cache_isolated) { - /* debug("ISOLATED write=%i cache=%i vaddr=%016llx " - "paddr=%016llx => addr in cache = 0x%lx\n", - writeflag, cache, (long long)vaddr, - (long long)paddr, addr); */ + /* debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" " + "paddr=%016"PRIx64" => addr in cache = 0x%lx\n", + writeflag, cache, (uint64_t) vaddr, + (uint64_t) paddr, addr); */ if (writeflag==MEM_READ) { for (i=0; i