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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: memory_mips.c,v 1.2 2005/11/30 16:23:09 debug Exp $ |
* $Id: memory_mips.c,v 1.7 2006/06/22 11:43:03 debug Exp $ |
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* |
* |
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* MIPS-specific memory routines. Included from cpu_mips.c. |
* MIPS-specific memory routines. Included from cpu_mips.c. |
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* |
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* NOTE: The cache emulation code (ifdef ENABLE_CACHE_EMULATION) is old |
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* and doesn't work with dyntrans. TODO: rewrite this. |
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*/ |
*/ |
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#include <sys/types.h> |
#include <sys/types.h> |
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/* |
/* |
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* insert_into_tiny_cache(): |
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* |
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* If the tiny cache is enabled (USE_TINY_CACHE), then this routine inserts |
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* a vaddr to paddr translation first in the instruction (or data) tiny |
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* translation cache. |
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*/ |
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static void insert_into_tiny_cache(struct cpu *cpu, int instr, int writeflag, |
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uint64_t vaddr, uint64_t paddr) |
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{ |
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#ifdef USE_TINY_CACHE |
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int wf = 1 + (writeflag == MEM_WRITE); |
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if (cpu->machine->bintrans_enable) |
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return; |
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paddr &= ~0xfff; |
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vaddr >>= 12; |
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if (instr) { |
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/* Code: */ |
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memmove(&cpu->cd.mips.translation_cache_instr[1], |
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&cpu->cd.mips.translation_cache_instr[0], |
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sizeof(struct translation_cache_entry) * |
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(N_TRANSLATION_CACHE_INSTR - 1)); |
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cpu->cd.mips.translation_cache_instr[0].wf = wf; |
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cpu->cd.mips.translation_cache_instr[0].vaddr_pfn = vaddr; |
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cpu->cd.mips.translation_cache_instr[0].paddr = paddr; |
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} else { |
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/* Data: */ |
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memmove(&cpu->cd.mips.translation_cache_data[1], |
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&cpu->cd.mips.translation_cache_data[0], |
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sizeof(struct translation_cache_entry) * |
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(N_TRANSLATION_CACHE_DATA - 1)); |
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cpu->cd.mips.translation_cache_data[0].wf = wf; |
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cpu->cd.mips.translation_cache_data[0].vaddr_pfn = vaddr; |
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cpu->cd.mips.translation_cache_data[0].paddr = paddr; |
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} |
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#endif |
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} |
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/* |
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* memory_cache_R3000(): |
* memory_cache_R3000(): |
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* |
* |
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* R2000/R3000 specific cache handling. |
* R2000/R3000 specific cache handling. |
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hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) && |
hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) && |
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(rp[cache_line].tag_paddr == (paddr & tag_mask)); |
(rp[cache_line].tag_paddr == (paddr & tag_mask)); |
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#ifdef ENABLE_INSTRUCTION_DELAYS |
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if (!hit) |
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cpu->cd.mips.instruction_delay += |
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cpu->cd.mips.cpu_type.instrs_per_cycle |
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* cpu->cd.mips.cache_miss_penalty[which_cache]; |
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#endif |
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/* |
/* |
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* The cache miss bit is only set on cache reads, and only to the |
* The cache miss bit is only set on cache reads, and only to the |
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* data cache. (?) |
* data cache. (?) |
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} |
} |
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} |
} |
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/* Run instructions from the right host page: */ |
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if (cache == CACHE_INSTRUCTION) { |
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memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
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if (memblock != NULL) { |
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cpu->cd.mips.pc_last_host_4k_page = memblock + |
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(paddr & ((1 << BITS_PER_MEMBLOCK) - 1) & ~0xfff); |
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} |
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} |
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/* Write-through! (Write to main memory as well.) */ |
/* Write-through! (Write to main memory as well.) */ |
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if (writeflag == MEM_READ || cache_isolated) |
if (writeflag == MEM_READ || cache_isolated) |
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return 1; |
return 1; |
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& ~cpu->cd.mips.cache_mask[which_cache]) |
& ~cpu->cd.mips.cache_mask[which_cache]) |
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== (paddr & ~(cpu->cd.mips.cache_mask[which_cache])); |
== (paddr & ~(cpu->cd.mips.cache_mask[which_cache])); |
228 |
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#ifdef ENABLE_INSTRUCTION_DELAYS |
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if (!hit) |
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cpu->cd.mips.instruction_delay += |
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cpu->cd.mips.cpu_type.instrs_per_cycle |
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* cpu->cd.mips.cache_miss_penalty[which_cache]; |
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#endif |
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229 |
/* |
/* |
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* The cache miss bit is only set on cache reads, and only to the |
* The cache miss bit is only set on cache reads, and only to the |
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* data cache. (?) |
* data cache. (?) |
250 |
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/* Data cache isolated? Then don't access main memory: */ |
/* Data cache isolated? Then don't access main memory: */ |
252 |
if (cache_isolated) { |
if (cache_isolated) { |
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/* debug("ISOLATED write=%i cache=%i vaddr=%016llx " |
/* debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" " |
254 |
"paddr=%016llx => addr in cache = 0x%lx\n", |
"paddr=%016"PRIx64" => addr in cache = 0x%lx\n", |
255 |
writeflag, cache, (long long)vaddr, |
writeflag, cache, (uint64_t) vaddr, |
256 |
(long long)paddr, addr); */ |
(uint64_t) paddr, addr); */ |
257 |
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258 |
if (writeflag==MEM_READ) { |
if (writeflag==MEM_READ) { |
259 |
for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
306 |
#include "memory_mips_v2p.c" |
#include "memory_mips_v2p.c" |
307 |
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308 |
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#ifndef EXPERIMENTAL_NEWMIPS |
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#define MEMORY_RW mips_memory_rw |
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#define MEM_MIPS |
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#include "../memory_rw.c" |
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#undef MEM_MIPS |
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#undef MEMORY_RW |
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#endif |
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