/[gxemul]/trunk/src/cpus/memory_mips.c
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Annotation of /trunk/src/cpus/memory_mips.c

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 8884 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 dpavlin 14 /*
2     * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 28 * $Id: memory_mips.c,v 1.9 2006/07/14 16:33:28 debug Exp $
29 dpavlin 14 *
30     * MIPS-specific memory routines. Included from cpu_mips.c.
31 dpavlin 24 *
32     * NOTE: The cache emulation code (ifdef ENABLE_CACHE_EMULATION) is old
33     * and doesn't work with dyntrans. TODO: rewrite this.
34 dpavlin 14 */
35    
36     #include <sys/types.h>
37     #include <sys/mman.h>
38    
39    
40     /*
41     * memory_cache_R3000():
42     *
43     * R2000/R3000 specific cache handling.
44     *
45     * Return value is 1 if a jump to do_return_ok is supposed to happen directly
46     * after this routine is finished, 0 otherwise.
47     */
48     int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
49     int writeflag, size_t len, unsigned char *data)
50     {
51     #ifdef ENABLE_CACHE_EMULATION
52     struct r3000_cache_line *rp;
53     int cache_line;
54     uint32_t tag_mask;
55     unsigned char *memblock;
56     struct memory *mem = cpu->mem;
57     #endif
58     unsigned int i;
59     int cache_isolated = 0, addr, hit, which_cache = cache;
60    
61    
62     if (len > 4 || cache == CACHE_NONE)
63     return 0;
64    
65    
66     #ifdef ENABLE_CACHE_EMULATION
67     if (cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_SWAP_CACHES)
68     which_cache ^= 1;
69    
70     tag_mask = 0xffffffff & ~cpu->cd.mips.cache_mask[which_cache];
71     cache_line = (paddr & cpu->cd.mips.cache_mask[which_cache])
72     / cpu->cd.mips.cache_linesize[which_cache];
73     rp = (struct r3000_cache_line *) cpu->cd.mips.cache_tags[which_cache];
74    
75     /* Is this a cache hit or miss? */
76     hit = (rp[cache_line].tag_valid & R3000_TAG_VALID) &&
77     (rp[cache_line].tag_paddr == (paddr & tag_mask));
78    
79     /*
80     * The cache miss bit is only set on cache reads, and only to the
81     * data cache. (?)
82     *
83     * (TODO: is this correct? I don't remember where I got this from.)
84     */
85     if (cache == CACHE_DATA && writeflag==MEM_READ) {
86     cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~MIPS1_CACHE_MISS;
87     if (!hit)
88     cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |=
89     MIPS1_CACHE_MISS;
90     }
91    
92     /*
93     * Is the Data cache isolated? Then don't access main memory:
94     */
95     if (cache == CACHE_DATA &&
96     cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)
97     cache_isolated = 1;
98    
99     addr = paddr & cpu->cd.mips.cache_mask[which_cache];
100    
101     /*
102     * If there was a miss and the cache is not isolated, then flush
103     * the old cacheline back to main memory, and read in the new
104     * cacheline.
105     *
106     * Then access the cache.
107     */
108     /*
109     fatal("L1 CACHE isolated=%i hit=%i write=%i cache=%i cacheline=%i"
110     " paddr=%08x => addr in"
111     " cache = 0x%lx\n", cache_isolated, hit, writeflag,
112     which_cache, cache_line, (int)paddr,
113     addr);
114     */
115     if (!hit && !cache_isolated) {
116     unsigned char *dst, *src;
117     uint64_t old_cached_paddr = rp[cache_line].tag_paddr
118     + cache_line * cpu->cd.mips.cache_linesize[which_cache];
119    
120     /* Flush the old cacheline to main memory: */
121     if ((rp[cache_line].tag_valid & R3000_TAG_VALID) &&
122     (rp[cache_line].tag_valid & R3000_TAG_DIRTY)) {
123     /* fatal(" FLUSHING old tag=0%08x "
124     "old_cached_paddr=0x%08x\n",
125     rp[cache_line].tag_paddr,
126     old_cached_paddr);
127     */
128     memblock = memory_paddr_to_hostaddr(
129 dpavlin 28 mem, old_cached_paddr & ~cpu->cd.mips.
130     cache_mask[which_cache], MEM_WRITE);
131 dpavlin 14
132     src = cpu->cd.mips.cache[which_cache];
133 dpavlin 28 dst = memblock;
134 dpavlin 14
135     src += cache_line *
136     cpu->cd.mips.cache_linesize[which_cache];
137     dst += cache_line *
138     cpu->cd.mips.cache_linesize[which_cache];
139    
140     if (memblock == NULL) {
141     fatal("BUG in memory.c! Hm.\n");
142     } else {
143     memcpy(dst, src,
144     cpu->cd.mips.cache_linesize[which_cache]);
145     }
146     }
147    
148     /* Copy from main memory into the cache: */
149 dpavlin 28 memblock = memory_paddr_to_hostaddr(mem, paddr
150     & ~cpu->cd.mips.cache_mask[which_cache], writeflag);
151 dpavlin 14
152     /* fatal(" FETCHING new paddr=0%08x\n", paddr);
153     */
154     dst = cpu->cd.mips.cache[which_cache];
155    
156     if (memblock == NULL) {
157     if (writeflag == MEM_READ)
158     memset(dst, 0,
159     cpu->cd.mips.cache_linesize[which_cache]);
160     } else {
161 dpavlin 28 src = memblock;
162 dpavlin 14
163     src += cache_line *
164     cpu->cd.mips.cache_linesize[which_cache];
165     dst += cache_line *
166     cpu->cd.mips.cache_linesize[which_cache];
167     memcpy(dst, src,
168     cpu->cd.mips.cache_linesize[which_cache]);
169     }
170    
171     rp[cache_line].tag_paddr = paddr & tag_mask;
172     rp[cache_line].tag_valid = R3000_TAG_VALID;
173     }
174    
175     if (cache_isolated && writeflag == MEM_WRITE) {
176     rp[cache_line].tag_valid = 0;
177     }
178    
179     if (writeflag==MEM_READ) {
180     for (i=0; i<len; i++)
181     data[i] = cpu->cd.mips.cache[which_cache][(addr+i) &
182     cpu->cd.mips.cache_mask[which_cache]];
183     } else {
184     for (i=0; i<len; i++) {
185     if (cpu->cd.mips.cache[which_cache][(addr+i) &
186     cpu->cd.mips.cache_mask[which_cache]] != data[i]) {
187     rp[cache_line].tag_valid |= R3000_TAG_DIRTY;
188     }
189     cpu->cd.mips.cache[which_cache][(addr+i) &
190     cpu->cd.mips.cache_mask[which_cache]] = data[i];
191     }
192     }
193    
194     /* Write-through! (Write to main memory as well.) */
195     if (writeflag == MEM_READ || cache_isolated)
196     return 1;
197    
198     #else
199    
200     /*
201     * R2000/R3000 without correct cache emulation:
202     *
203     * TODO: This is just enough to trick NetBSD/pmax and Ultrix into
204     * being able to detect the cache sizes and think that the caches
205     * are actually working, but they are not.
206     */
207    
208     if (cache != CACHE_DATA)
209     return 0;
210    
211     /* Is this a cache hit or miss? */
212     hit = (cpu->cd.mips.cache_last_paddr[which_cache]
213     & ~cpu->cd.mips.cache_mask[which_cache])
214     == (paddr & ~(cpu->cd.mips.cache_mask[which_cache]));
215    
216     /*
217     * The cache miss bit is only set on cache reads, and only to the
218     * data cache. (?)
219     *
220     * (TODO: is this correct? I don't remember where I got this from.)
221     */
222     if (cache == CACHE_DATA && writeflag==MEM_READ) {
223     cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~MIPS1_CACHE_MISS;
224     if (!hit)
225     cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |=
226     MIPS1_CACHE_MISS;
227     }
228    
229     /*
230     * Is the Data cache isolated? Then don't access main memory:
231     */
232     if (cache == CACHE_DATA &&
233     cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)
234     cache_isolated = 1;
235    
236     addr = paddr & cpu->cd.mips.cache_mask[which_cache];
237    
238     /* Data cache isolated? Then don't access main memory: */
239     if (cache_isolated) {
240 dpavlin 24 /* debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" "
241     "paddr=%016"PRIx64" => addr in cache = 0x%lx\n",
242     writeflag, cache, (uint64_t) vaddr,
243     (uint64_t) paddr, addr); */
244 dpavlin 14
245     if (writeflag==MEM_READ) {
246     for (i=0; i<len; i++)
247     data[i] = cpu->cd.mips.cache[cache][(addr+i) &
248     cpu->cd.mips.cache_mask[cache]];
249     } else {
250     for (i=0; i<len; i++)
251     cpu->cd.mips.cache[cache][(addr+i) &
252     cpu->cd.mips.cache_mask[cache]] = data[i];
253     }
254     return 1;
255     } else {
256     /* Reload caches if necessary: */
257    
258     /* No! Not when not emulating caches fully. (TODO?) */
259     cpu->cd.mips.cache_last_paddr[cache] = paddr;
260     }
261     #endif
262    
263     return 0;
264     }
265    
266    
267 dpavlin 26 #define TRANSLATE_ADDRESS translate_v2p_mmu3k
268 dpavlin 14 #define V2P_MMU3K
269     #include "memory_mips_v2p.c"
270     #undef TRANSLATE_ADDRESS
271     #undef V2P_MMU3K
272    
273 dpavlin 26 #define TRANSLATE_ADDRESS translate_v2p_mmu8k
274 dpavlin 14 #define V2P_MMU8K
275     #include "memory_mips_v2p.c"
276     #undef TRANSLATE_ADDRESS
277     #undef V2P_MMU8K
278    
279 dpavlin 26 #define TRANSLATE_ADDRESS translate_v2p_mmu10k
280 dpavlin 14 #define V2P_MMU10K
281     #include "memory_mips_v2p.c"
282     #undef TRANSLATE_ADDRESS
283     #undef V2P_MMU10K
284    
285     /* Almost generic :-) */
286 dpavlin 26 #define TRANSLATE_ADDRESS translate_v2p_mmu4100
287 dpavlin 14 #define V2P_MMU4100
288     #include "memory_mips_v2p.c"
289     #undef TRANSLATE_ADDRESS
290     #undef V2P_MMU4100
291    
292 dpavlin 26 #define TRANSLATE_ADDRESS translate_v2p_generic
293 dpavlin 14 #include "memory_mips_v2p.c"
294    
295    

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