/[gxemul]/trunk/src/cpus/memory_fast_v2h.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/memory_fast_v2h.c

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Revision 14 - (hide annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 6909 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.
1 dpavlin 14 /*
2     * Copyright (C) 2004-2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28     * $Id: memory_fast_v2h.c,v 1.1 2005/08/29 14:36:42 debug Exp $
29     *
30     * Fast virtual memory to host address, used by binary translated code.
31     */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35    
36     #include "bintrans.h"
37     #include "cpu.h"
38     #include "memory.h"
39     #include "cpu_mips.h"
40     #include "misc.h"
41    
42    
43     #ifdef BINTRANS
44    
45     /*
46     * fast_vaddr_to_hostaddr():
47     *
48     * Used by dynamically translated code. The caller should have made sure
49     * that the access is aligned correctly.
50     *
51     * Return value is a pointer to a host page + offset, if the page was
52     * writable (or writeflag was zero), if the virtual address was translatable
53     * to a paddr, and if the paddr was translatable to a host address.
54     *
55     * On error, NULL is returned. The caller (usually the dynamically
56     * generated machine code) must check for this.
57     */
58     unsigned char *fast_vaddr_to_hostaddr(struct cpu *cpu,
59     uint64_t vaddr, int writeflag)
60     {
61     int ok, i, n, start_and_stop;
62     uint64_t paddr, vaddr_page;
63     unsigned char *memblock;
64     size_t offset;
65     const int MAX = N_BINTRANS_VADDR_TO_HOST;
66    
67     /* printf("fast_vaddr_to_hostaddr(): cpu=%p, vaddr=%016llx, wf=%i\n",
68     cpu, (long long)vaddr, writeflag); */
69    
70     #if 0
71     /* Hm. This seems to work now, so this #if X can be removed. (?) */
72    
73     /*
74     * TODO:
75     *
76     * Why doesn't this work yet?
77     */
78     if ((vaddr & 0xc0000000ULL) >= 0xc0000000ULL && writeflag) {
79     return NULL;
80     }
81     #endif
82    
83    
84     vaddr_page = vaddr & ~0xfff;
85     i = start_and_stop = cpu->cd.mips.bintrans_next_index;
86     n = 0;
87     for (;;) {
88     if (cpu->cd.mips.bintrans_data_vaddr[i] == vaddr_page &&
89     cpu->cd.mips.bintrans_data_hostpage[i] != NULL &&
90     cpu->cd.mips.bintrans_data_writable[i] >= writeflag) {
91     uint64_t tmpaddr;
92     unsigned char *tmpptr;
93     int tmpwf;
94    
95     if (n < 3)
96     return cpu->cd.mips.bintrans_data_hostpage[i]
97     + (vaddr & 0xfff);
98    
99     cpu->cd.mips.bintrans_next_index = start_and_stop - 1;
100     if (cpu->cd.mips.bintrans_next_index < 0)
101     cpu->cd.mips.bintrans_next_index = MAX - 1;
102    
103     tmpptr = cpu->cd.mips.bintrans_data_hostpage[
104     cpu->cd.mips.bintrans_next_index];
105     tmpaddr = cpu->cd.mips.bintrans_data_vaddr[
106     cpu->cd.mips.bintrans_next_index];
107     tmpwf = cpu->cd.mips.bintrans_data_writable[
108     cpu->cd.mips.bintrans_next_index];
109    
110     cpu->cd.mips.bintrans_data_hostpage[
111     cpu->cd.mips.bintrans_next_index] =
112     cpu->cd.mips.bintrans_data_hostpage[i];
113     cpu->cd.mips.bintrans_data_vaddr[
114     cpu->cd.mips.bintrans_next_index] =
115     cpu->cd.mips.bintrans_data_vaddr[i];
116     cpu->cd.mips.bintrans_data_writable[
117     cpu->cd.mips.bintrans_next_index] =
118     cpu->cd.mips.bintrans_data_writable[i];
119    
120     cpu->cd.mips.bintrans_data_hostpage[i] = tmpptr;
121     cpu->cd.mips.bintrans_data_vaddr[i] = tmpaddr;
122     cpu->cd.mips.bintrans_data_writable[i] = tmpwf;
123    
124     return cpu->cd.mips.bintrans_data_hostpage[
125     cpu->cd.mips.bintrans_next_index] + (vaddr & 0xfff);
126     }
127    
128     n ++;
129     i ++;
130     if (i == MAX)
131     i = 0;
132     if (i == start_and_stop)
133     break;
134     }
135    
136     ok = cpu->translate_address(cpu, vaddr, &paddr,
137     (writeflag? FLAG_WRITEFLAG : 0) + FLAG_NOEXCEPTIONS);
138     /* printf("ok=%i\n", ok); */
139     if (!ok)
140     return NULL;
141    
142     for (i=0; i<cpu->mem->n_mmapped_devices; i++)
143     if (paddr >= (cpu->mem->dev_baseaddr[i] & ~0xfff) &&
144     paddr <= ((cpu->mem->dev_baseaddr[i] +
145     cpu->mem->dev_length[i] - 1) | 0xfff)) {
146     if (cpu->mem->dev_flags[i] & MEM_DYNTRANS_OK) {
147     paddr -= cpu->mem->dev_baseaddr[i];
148    
149     /* Within a device _page_ but not within the
150     actual device? Then abort: */
151     if ((int64_t)paddr < 0 ||
152     paddr >= cpu->mem->dev_length[i])
153     return NULL;
154    
155     if (writeflag) {
156     uint64_t low_paddr = paddr & ~0xfff;
157     uint64_t high_paddr = paddr | 0xfff;
158     if (!(cpu->mem->dev_flags[i] &
159     MEM_DYNTRANS_WRITE_OK))
160     return NULL;
161    
162     if (low_paddr < cpu->mem->
163     dev_dyntrans_write_low[i])
164     cpu->mem->
165     dev_dyntrans_write_low[i] =
166     low_paddr;
167     if (high_paddr > cpu->mem->
168     dev_dyntrans_write_high[i])
169     cpu->mem->
170     dev_dyntrans_write_high[i]
171     = high_paddr;
172     }
173    
174     cpu->cd.mips.bintrans_next_index --;
175     if (cpu->cd.mips.bintrans_next_index < 0)
176     cpu->cd.mips.bintrans_next_index =
177     MAX - 1;
178     cpu->cd.mips.bintrans_data_hostpage[cpu->
179     cd.mips.bintrans_next_index] = cpu->mem->
180     dev_dyntrans_data[i] + (paddr & ~0xfff);
181     cpu->cd.mips.bintrans_data_vaddr[cpu->
182     cd.mips.bintrans_next_index] = vaddr_page;
183     cpu->cd.mips.bintrans_data_writable[cpu->
184     cd.mips.bintrans_next_index] = writeflag;
185     return cpu->mem->dev_dyntrans_data[i] + paddr;
186     } else
187     return NULL;
188     }
189    
190     memblock = memory_paddr_to_hostaddr(cpu->mem, paddr,
191     writeflag? MEM_WRITE : MEM_READ);
192     if (memblock == NULL)
193     return NULL;
194    
195     offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1);
196    
197     if (writeflag)
198     bintrans_invalidate(cpu, paddr);
199    
200     cpu->cd.mips.bintrans_next_index --;
201     if (cpu->cd.mips.bintrans_next_index < 0)
202     cpu->cd.mips.bintrans_next_index = MAX - 1;
203     cpu->cd.mips.bintrans_data_hostpage[cpu->cd.mips.bintrans_next_index] =
204     memblock + (offset & ~0xfff);
205     cpu->cd.mips.bintrans_data_vaddr[cpu->cd.mips.bintrans_next_index] =
206     vaddr_page;
207     cpu->cd.mips.bintrans_data_writable[cpu->cd.mips.bintrans_next_index] =
208     writeflag; /* ok - 1; */
209    
210     return memblock + offset;
211     }
212    
213     #endif /* BINTRANS */
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