/[gxemul]/trunk/src/cpus/memory_arm.c
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Contents of /trunk/src/cpus/memory_arm.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 8012 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: memory_arm.c,v 1.33 2006/01/25 05:51:12 debug Exp $
29 *
30 *
31 * TODO/NOTE: The B and/or C bits could also cause the return value to
32 * be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the
33 * translation arrays. TODO: Find out if this is a good thing to do.
34 */
35
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39
40 #include "arm_cpu_types.h"
41 #include "cpu.h"
42 #include "memory.h"
43 #include "misc.h"
44
45 #include "armreg.h"
46
47 extern int quiet_mode;
48
49
50 /*
51 * arm_translate_address():
52 *
53 * Address translation with the MMU disabled.
54 */
55 int arm_translate_address(struct cpu *cpu, uint64_t vaddr64,
56 uint64_t *return_addr, int flags)
57 {
58 *return_addr = vaddr64 & 0xffffffff;
59 return 2;
60 }
61
62
63 /*
64 * arm_check_access():
65 *
66 * Helper function. Returns 0 for no access, 1 for read-only, and 2 for
67 * read/write.
68 */
69 static int arm_check_access(struct cpu *cpu, int ap, int dav, int user)
70 {
71 int s, r;
72
73 switch (dav) {
74 case 0: /* No access at all. */
75 return 0;
76 case 1: /* Normal access check. */
77 break;
78 case 2: fatal("arm_check_access(): 1 shouldn't be used\n");
79 exit(1);
80 case 3: /* Anything is allowed. */
81 return 2;
82 }
83
84 switch (ap) {
85 case 0: s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0;
86 r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0;
87 switch (s + r) {
88 case 0: return 0;
89 case 1: return user? 0 : 1;
90 case 2: return 1;
91 }
92 fatal("arm_check_access: UNPREDICTABLE s+r value!\n");
93 return 0;
94 case 1: return user? 0 : 2;
95 case 2: return user? 1 : 2;
96 }
97
98 /* "case 3": */
99 return 2;
100 }
101
102
103 /*
104 * arm_translate_address_mmu():
105 *
106 * Don't call this function is userland_emul is non-NULL, or cpu is NULL.
107 *
108 * Return values:
109 * 0 Failure
110 * 1 Success, the page is readable only
111 * 2 Success, the page is read/write
112 *
113 * If this is a 1KB page access, then the return value is ORed with
114 * MEMORY_NOT_FULL_PAGE.
115 */
116 int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr64,
117 uint64_t *return_addr, int flags)
118 {
119 unsigned char *q;
120 uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64;
121 int instr = flags & FLAG_INSTR;
122 int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
123 int useraccess = flags & MEMORY_USER_ACCESS;
124 int no_exceptions = flags & FLAG_NOEXCEPTIONS;
125 int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32;
126 int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0;
127 int fs = 2; /* fault status (2 = terminal exception) */
128 int subpage = 0;
129
130 if (useraccess)
131 user = 1;
132
133 addr = ((vaddr & 0xfff00000ULL) >> 18);
134
135 if (cpu->cd.arm.translation_table == NULL ||
136 cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) {
137 uint32_t ofs;
138 cpu->cd.arm.translation_table = memory_paddr_to_hostaddr(
139 cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0);
140 if (cpu->cd.arm.translation_table != NULL) {
141 ofs = cpu->cd.arm.ttb & ((1 << BITS_PER_MEMBLOCK) - 1);
142 cpu->cd.arm.translation_table += ofs;
143 }
144 cpu->cd.arm.last_ttb = cpu->cd.arm.ttb;
145 }
146
147 if (cpu->cd.arm.translation_table != NULL) {
148 d = *(uint32_t *)(cpu->cd.arm.translation_table + addr);
149 #ifdef HOST_LITTLE_ENDIAN
150 if (cpu->byte_order == EMUL_BIG_ENDIAN)
151 #else
152 if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
153 #endif
154 d = ((d & 0xff) << 24) | ((d & 0xff00) << 8) |
155 ((d & 0xff0000) >> 8) | ((d & 0xff000000) >> 24);
156 }
157
158 /* Get the domain from the descriptor, and the Domain Access Value: */
159 domain = (d >> 5) & 15;
160 dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3;
161
162 switch (d & 3) {
163
164 case 0: domain = 0;
165 fs = FAULT_TRANS_S;
166 goto exception_return;
167
168 case 1: /* Course Pagetable: */
169 if (dav == 0) {
170 fs = FAULT_DOMAIN_P;
171 goto exception_return;
172 }
173 ptba = d & 0xfffffc00;
174 addr = ptba + ((vaddr & 0x000ff000) >> 10);
175
176 q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0);
177 if (q == NULL) {
178 printf("arm memory blah blah adfh asfg asdgasdg\n");
179 exit(1);
180 }
181 d2 = *(uint32_t *)(q + (addr & ((1 << BITS_PER_MEMBLOCK) - 1)));
182 #ifdef HOST_LITTLE_ENDIAN
183 if (cpu->byte_order == EMUL_BIG_ENDIAN)
184 #else
185 if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
186 #endif
187 d2 = ((d2 & 0xff) << 24) | ((d2 & 0xff00) << 8) |
188 ((d2 & 0xff0000) >> 8) | ((d2 & 0xff000000) >> 24);
189
190 switch (d2 & 3) {
191 case 0: fs = FAULT_TRANS_P;
192 goto exception_return;
193 case 1: /* 16KB page: */
194 ap = (d2 >> 4) & 255;
195 switch (vaddr & 0x0000c000) {
196 case 0x4000: ap >>= 2; break;
197 case 0x8000: ap >>= 4; break;
198 case 0xc000: ap >>= 6; break;
199 }
200 ap &= 3;
201 *return_addr = (d2 & 0xffff0000) | (vaddr & 0x0000ffff);
202 break;
203 case 3: if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
204 /* 4KB page (Xscale) */
205 subpage = 0;
206 } else {
207 /* 1KB page */
208 subpage = 1;
209 ap = (d2 >> 4) & 3;
210 *return_addr = (d2 & 0xfffffc00) |
211 (vaddr & 0x000003ff);
212 break;
213 }
214 /* NOTE: Fall-through for XScale! */
215 case 2: /* 4KB page: */
216 ap3 = (d2 >> 10) & 3;
217 ap2 = (d2 >> 8) & 3;
218 ap1 = (d2 >> 6) & 3;
219 ap0 = (d2 >> 4) & 3;
220 switch (vaddr & 0x00000c00) {
221 case 0x000: ap = ap0; break;
222 case 0x400: ap = ap1; break;
223 case 0x800: ap = ap2; break;
224 default: ap = ap3;
225 }
226 /* NOTE: Ugly hack for XScale: */
227 if ((d2 & 3) == 3) {
228 /* Treated as 4KB page: */
229 ap = ap0;
230 } else {
231 if (ap0 != ap1 || ap0 != ap2 || ap0 != ap3)
232 subpage = 1;
233 }
234 *return_addr = (d2 & 0xfffff000) | (vaddr & 0x00000fff);
235 break;
236 }
237 access = arm_check_access(cpu, ap, dav, user);
238 if (access > writeflag)
239 return access | (subpage? MEMORY_NOT_FULL_PAGE : 0);
240 fs = FAULT_PERM_P;
241 goto exception_return;
242
243 case 2: /* Section descriptor: */
244 if (dav == 0) {
245 fs = FAULT_DOMAIN_S;
246 goto exception_return;
247 }
248 *return_addr = (d & 0xfff00000) | (vaddr & 0x000fffff);
249 ap = (d >> 10) & 3;
250 access = arm_check_access(cpu, ap, dav, user);
251 if (access > writeflag)
252 return access;
253 fs = FAULT_PERM_S;
254 goto exception_return;
255
256 default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x ("
257 "unimplemented type %i)\n", vaddr, d, d&3);
258 exit(1);
259 }
260
261 exception_return:
262 if (no_exceptions)
263 return 0;
264
265 if (!quiet_mode) {
266 fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i "
267 "access=%i user=%i", (int)vaddr, domain, dav, ap,
268 access, user);
269 fatal(" d=0x%08x d2=0x%08x pc=0x%08x }\n", d, d2, (int)cpu->pc);
270 }
271
272 if (instr)
273 arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
274 else {
275 cpu->cd.arm.far = vaddr;
276 cpu->cd.arm.fsr = (domain << 4) | fs;
277 arm_exception(cpu, ARM_EXCEPTION_DATA_ABT);
278 }
279
280 return 0;
281 }
282

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