/[gxemul]/trunk/src/cpus/memory_arm.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 5 months ago) by dpavlin
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File size: 7856 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 dpavlin 14 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: memory_arm.c,v 1.38 2006/12/30 13:30:56 debug Exp $
29 dpavlin 14 *
30     *
31 dpavlin 18 * TODO/NOTE: The B and/or C bits could also cause the return value to
32     * be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the
33     * translation arrays. TODO: Find out if this is a good thing to do.
34 dpavlin 14 */
35    
36     #include <stdio.h>
37     #include <stdlib.h>
38     #include <string.h>
39    
40 dpavlin 22 #include "arm_cpu_types.h"
41 dpavlin 14 #include "cpu.h"
42     #include "memory.h"
43     #include "misc.h"
44    
45     #include "armreg.h"
46    
47     extern int quiet_mode;
48    
49    
50     /*
51 dpavlin 26 * arm_translate_v2p():
52 dpavlin 18 *
53 dpavlin 26 * Address translation with the MMU disabled. (Just treat the virtual address
54     * as a physical address.)
55 dpavlin 18 */
56 dpavlin 26 int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr64,
57     uint64_t *return_paddr, int flags)
58 dpavlin 18 {
59 dpavlin 26 *return_paddr = vaddr64 & 0xffffffff;
60    
61 dpavlin 18 return 2;
62     }
63    
64    
65     /*
66 dpavlin 14 * arm_check_access():
67     *
68     * Helper function. Returns 0 for no access, 1 for read-only, and 2 for
69     * read/write.
70     */
71     static int arm_check_access(struct cpu *cpu, int ap, int dav, int user)
72     {
73     int s, r;
74    
75     switch (dav) {
76     case 0: /* No access at all. */
77     return 0;
78     case 1: /* Normal access check. */
79     break;
80     case 2: fatal("arm_check_access(): 1 shouldn't be used\n");
81     exit(1);
82     case 3: /* Anything is allowed. */
83     return 2;
84     }
85    
86     switch (ap) {
87     case 0: s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0;
88     r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0;
89     switch (s + r) {
90     case 0: return 0;
91     case 1: return user? 0 : 1;
92     case 2: return 1;
93     }
94     fatal("arm_check_access: UNPREDICTABLE s+r value!\n");
95     return 0;
96     case 1: return user? 0 : 2;
97     case 2: return user? 1 : 2;
98     }
99    
100     /* "case 3": */
101     return 2;
102     }
103    
104    
105     /*
106 dpavlin 26 * arm_translate_v2p_mmu():
107 dpavlin 14 *
108 dpavlin 32 * Don't call this function if userland_emul is non-NULL, or cpu is NULL.
109 dpavlin 14 *
110     * Return values:
111     * 0 Failure
112     * 1 Success, the page is readable only
113     * 2 Success, the page is read/write
114 dpavlin 18 *
115     * If this is a 1KB page access, then the return value is ORed with
116     * MEMORY_NOT_FULL_PAGE.
117 dpavlin 14 */
118 dpavlin 26 int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr64,
119     uint64_t *return_paddr, int flags)
120 dpavlin 14 {
121 dpavlin 18 unsigned char *q;
122     uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64;
123 dpavlin 14 int instr = flags & FLAG_INSTR;
124     int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
125     int useraccess = flags & MEMORY_USER_ACCESS;
126     int no_exceptions = flags & FLAG_NOEXCEPTIONS;
127     int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32;
128     int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0;
129     int fs = 2; /* fault status (2 = terminal exception) */
130 dpavlin 18 int subpage = 0;
131 dpavlin 14
132     if (useraccess)
133     user = 1;
134    
135 dpavlin 18 addr = ((vaddr & 0xfff00000ULL) >> 18);
136    
137     if (cpu->cd.arm.translation_table == NULL ||
138     cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) {
139     cpu->cd.arm.translation_table = memory_paddr_to_hostaddr(
140     cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0);
141     cpu->cd.arm.last_ttb = cpu->cd.arm.ttb;
142 dpavlin 14 }
143    
144 dpavlin 18 if (cpu->cd.arm.translation_table != NULL) {
145     d = *(uint32_t *)(cpu->cd.arm.translation_table + addr);
146     #ifdef HOST_LITTLE_ENDIAN
147     if (cpu->byte_order == EMUL_BIG_ENDIAN)
148     #else
149     if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
150     #endif
151     d = ((d & 0xff) << 24) | ((d & 0xff00) << 8) |
152     ((d & 0xff0000) >> 8) | ((d & 0xff000000) >> 24);
153     }
154 dpavlin 14
155     /* Get the domain from the descriptor, and the Domain Access Value: */
156     domain = (d >> 5) & 15;
157     dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3;
158    
159     switch (d & 3) {
160    
161 dpavlin 18 case 0: domain = 0;
162 dpavlin 14 fs = FAULT_TRANS_S;
163     goto exception_return;
164    
165     case 1: /* Course Pagetable: */
166 dpavlin 18 if (dav == 0) {
167     fs = FAULT_DOMAIN_P;
168     goto exception_return;
169     }
170 dpavlin 14 ptba = d & 0xfffffc00;
171     addr = ptba + ((vaddr & 0x000ff000) >> 10);
172 dpavlin 18
173     q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0);
174     if (q == NULL) {
175     printf("arm memory blah blah adfh asfg asdgasdg\n");
176 dpavlin 14 exit(1);
177     }
178 dpavlin 28 d2 = *(uint32_t *)(q);
179 dpavlin 18 #ifdef HOST_LITTLE_ENDIAN
180     if (cpu->byte_order == EMUL_BIG_ENDIAN)
181     #else
182 dpavlin 14 if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
183 dpavlin 18 #endif
184     d2 = ((d2 & 0xff) << 24) | ((d2 & 0xff00) << 8) |
185     ((d2 & 0xff0000) >> 8) | ((d2 & 0xff000000) >> 24);
186 dpavlin 14
187     switch (d2 & 3) {
188     case 0: fs = FAULT_TRANS_P;
189     goto exception_return;
190     case 1: /* 16KB page: */
191     ap = (d2 >> 4) & 255;
192     switch (vaddr & 0x0000c000) {
193     case 0x4000: ap >>= 2; break;
194     case 0x8000: ap >>= 4; break;
195     case 0xc000: ap >>= 6; break;
196     }
197     ap &= 3;
198 dpavlin 26 *return_paddr = (d2 & 0xffff0000)|(vaddr & 0x0000ffff);
199 dpavlin 14 break;
200 dpavlin 22 case 3: if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
201     /* 4KB page (Xscale) */
202     subpage = 0;
203     } else {
204     /* 1KB page */
205     subpage = 1;
206     ap = (d2 >> 4) & 3;
207 dpavlin 26 *return_paddr = (d2 & 0xfffffc00) |
208 dpavlin 22 (vaddr & 0x000003ff);
209     break;
210 dpavlin 20 }
211 dpavlin 22 /* NOTE: Fall-through for XScale! */
212 dpavlin 14 case 2: /* 4KB page: */
213     ap3 = (d2 >> 10) & 3;
214     ap2 = (d2 >> 8) & 3;
215     ap1 = (d2 >> 6) & 3;
216     ap0 = (d2 >> 4) & 3;
217     switch (vaddr & 0x00000c00) {
218     case 0x000: ap = ap0; break;
219     case 0x400: ap = ap1; break;
220     case 0x800: ap = ap2; break;
221     default: ap = ap3;
222     }
223 dpavlin 22 /* NOTE: Ugly hack for XScale: */
224     if ((d2 & 3) == 3) {
225     /* Treated as 4KB page: */
226 dpavlin 20 ap = ap0;
227 dpavlin 22 } else {
228     if (ap0 != ap1 || ap0 != ap2 || ap0 != ap3)
229     subpage = 1;
230     }
231 dpavlin 26 *return_paddr = (d2 & 0xfffff000)|(vaddr & 0x00000fff);
232 dpavlin 14 break;
233     }
234     access = arm_check_access(cpu, ap, dav, user);
235     if (access > writeflag)
236 dpavlin 18 return access | (subpage? MEMORY_NOT_FULL_PAGE : 0);
237 dpavlin 14 fs = FAULT_PERM_P;
238     goto exception_return;
239    
240     case 2: /* Section descriptor: */
241     if (dav == 0) {
242     fs = FAULT_DOMAIN_S;
243     goto exception_return;
244     }
245 dpavlin 26 *return_paddr = (d & 0xfff00000) | (vaddr & 0x000fffff);
246 dpavlin 14 ap = (d >> 10) & 3;
247     access = arm_check_access(cpu, ap, dav, user);
248     if (access > writeflag)
249     return access;
250     fs = FAULT_PERM_S;
251     goto exception_return;
252    
253     default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x ("
254     "unimplemented type %i)\n", vaddr, d, d&3);
255     exit(1);
256     }
257    
258     exception_return:
259     if (no_exceptions)
260     return 0;
261    
262     if (!quiet_mode) {
263     fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i "
264     "access=%i user=%i", (int)vaddr, domain, dav, ap,
265     access, user);
266 dpavlin 22 fatal(" d=0x%08x d2=0x%08x pc=0x%08x }\n", d, d2, (int)cpu->pc);
267 dpavlin 14 }
268    
269     if (instr)
270     arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
271     else {
272     cpu->cd.arm.far = vaddr;
273     cpu->cd.arm.fsr = (domain << 4) | fs;
274     arm_exception(cpu, ARM_EXCEPTION_DATA_ABT);
275     }
276    
277     return 0;
278     }
279    

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