/[gxemul]/trunk/src/cpus/memory_arm.c
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Contents of /trunk/src/cpus/memory_arm.c

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (14 years, 2 months ago) by dpavlin
File MIME type: text/plain
File size: 7973 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: memory_arm.c,v 1.30 2005/11/05 17:56:46 debug Exp $
29 *
30 *
31 * TODO/NOTE: The B and/or C bits could also cause the return value to
32 * be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the
33 * translation arrays. TODO: Find out if this is a good thing to do.
34 */
35
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39
40 #include "cpu.h"
41 #include "memory.h"
42 #include "misc.h"
43
44 #include "armreg.h"
45
46 extern int quiet_mode;
47
48
49 /*
50 * arm_translate_address():
51 *
52 * Address translation with the MMU disabled.
53 */
54 int arm_translate_address(struct cpu *cpu, uint64_t vaddr64,
55 uint64_t *return_addr, int flags)
56 {
57 *return_addr = vaddr64 & 0xffffffff;
58 return 2;
59 }
60
61
62 /*
63 * arm_check_access():
64 *
65 * Helper function. Returns 0 for no access, 1 for read-only, and 2 for
66 * read/write.
67 */
68 static int arm_check_access(struct cpu *cpu, int ap, int dav, int user)
69 {
70 int s, r;
71
72 switch (dav) {
73 case 0: /* No access at all. */
74 return 0;
75 case 1: /* Normal access check. */
76 break;
77 case 2: fatal("arm_check_access(): 1 shouldn't be used\n");
78 exit(1);
79 case 3: /* Anything is allowed. */
80 return 2;
81 }
82
83 switch (ap) {
84 case 0: s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0;
85 r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0;
86 switch (s + r) {
87 case 0: return 0;
88 case 1: return user? 0 : 1;
89 case 2: return 1;
90 }
91 fatal("arm_check_access: UNPREDICTABLE s+r value!\n");
92 return 0;
93 case 1: return user? 0 : 2;
94 case 2: return user? 1 : 2;
95 }
96
97 /* "case 3": */
98 return 2;
99 }
100
101
102 /*
103 * arm_translate_address_mmu():
104 *
105 * Don't call this function is userland_emul is non-NULL, or cpu is NULL.
106 *
107 * Return values:
108 * 0 Failure
109 * 1 Success, the page is readable only
110 * 2 Success, the page is read/write
111 *
112 * If this is a 1KB page access, then the return value is ORed with
113 * MEMORY_NOT_FULL_PAGE.
114 */
115 int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr64,
116 uint64_t *return_addr, int flags)
117 {
118 unsigned char *q;
119 uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64;
120 int instr = flags & FLAG_INSTR;
121 int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
122 int useraccess = flags & MEMORY_USER_ACCESS;
123 int no_exceptions = flags & FLAG_NOEXCEPTIONS;
124 int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32;
125 int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0;
126 int fs = 2; /* fault status (2 = terminal exception) */
127 int subpage = 0;
128
129 if (useraccess)
130 user = 1;
131
132 addr = ((vaddr & 0xfff00000ULL) >> 18);
133
134 if (cpu->cd.arm.translation_table == NULL ||
135 cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) {
136 uint32_t ofs;
137 cpu->cd.arm.translation_table = memory_paddr_to_hostaddr(
138 cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0);
139 if (cpu->cd.arm.translation_table != NULL) {
140 ofs = cpu->cd.arm.ttb & ((1 << BITS_PER_MEMBLOCK) - 1);
141 cpu->cd.arm.translation_table += ofs;
142 }
143 cpu->cd.arm.last_ttb = cpu->cd.arm.ttb;
144 }
145
146 if (cpu->cd.arm.translation_table != NULL) {
147 d = *(uint32_t *)(cpu->cd.arm.translation_table + addr);
148 #ifdef HOST_LITTLE_ENDIAN
149 if (cpu->byte_order == EMUL_BIG_ENDIAN)
150 #else
151 if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
152 #endif
153 d = ((d & 0xff) << 24) | ((d & 0xff00) << 8) |
154 ((d & 0xff0000) >> 8) | ((d & 0xff000000) >> 24);
155 }
156
157 /* Get the domain from the descriptor, and the Domain Access Value: */
158 domain = (d >> 5) & 15;
159 dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3;
160
161 switch (d & 3) {
162
163 case 0: domain = 0;
164 fs = FAULT_TRANS_S;
165 goto exception_return;
166
167 case 1: /* Course Pagetable: */
168 if (dav == 0) {
169 fs = FAULT_DOMAIN_P;
170 goto exception_return;
171 }
172 ptba = d & 0xfffffc00;
173 addr = ptba + ((vaddr & 0x000ff000) >> 10);
174
175 q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0);
176 if (q == NULL) {
177 printf("arm memory blah blah adfh asfg asdgasdg\n");
178 exit(1);
179 }
180 d2 = *(uint32_t *)(q + (addr & ((1 << BITS_PER_MEMBLOCK) - 1)));
181 #ifdef HOST_LITTLE_ENDIAN
182 if (cpu->byte_order == EMUL_BIG_ENDIAN)
183 #else
184 if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
185 #endif
186 d2 = ((d2 & 0xff) << 24) | ((d2 & 0xff00) << 8) |
187 ((d2 & 0xff0000) >> 8) | ((d2 & 0xff000000) >> 24);
188
189 switch (d2 & 3) {
190 case 0: fs = FAULT_TRANS_P;
191 goto exception_return;
192 case 1: /* 16KB page: */
193 ap = (d2 >> 4) & 255;
194 switch (vaddr & 0x0000c000) {
195 case 0x4000: ap >>= 2; break;
196 case 0x8000: ap >>= 4; break;
197 case 0xc000: ap >>= 6; break;
198 }
199 ap &= 3;
200 *return_addr = (d2 & 0xffff0000) | (vaddr & 0x0000ffff);
201 break;
202 case 3: {
203 static int first = 1;
204 if (first) {
205 fatal("[ WARNING! ARM course second "
206 "level page table seems to contain"
207 " tiny pages; treating as 4K ]\n");
208 first = 0;
209 }
210 }
211 subpage = 1;
212 case 2: /* 4KB page: */
213 ap3 = (d2 >> 10) & 3;
214 ap2 = (d2 >> 8) & 3;
215 ap1 = (d2 >> 6) & 3;
216 ap0 = (d2 >> 4) & 3;
217 switch (vaddr & 0x00000c00) {
218 case 0x000: ap = ap0; break;
219 case 0x400: ap = ap1; break;
220 case 0x800: ap = ap2; break;
221 default: ap = ap3;
222 }
223 /* Ugly hack: (TODO) */
224 if ((d2 & 3) == 3)
225 ap = ap0;
226 if (ap0 != ap1 || ap0 != ap2 || ap0 != ap3)
227 subpage = 1;
228 *return_addr = (d2 & 0xfffff000) | (vaddr & 0x00000fff);
229 break;
230 #if 0
231 case 3: /* 1KB page: */
232 subpage = 1;
233 ap = (d2 >> 4) & 3;
234 *return_addr = (d2 & 0xfffffc00) | (vaddr & 0x000003ff);
235 break;
236 #endif
237 }
238 access = arm_check_access(cpu, ap, dav, user);
239 if (access > writeflag)
240 return access | (subpage? MEMORY_NOT_FULL_PAGE : 0);
241 fs = FAULT_PERM_P;
242 goto exception_return;
243
244 case 2: /* Section descriptor: */
245 if (dav == 0) {
246 fs = FAULT_DOMAIN_S;
247 goto exception_return;
248 }
249 *return_addr = (d & 0xfff00000) | (vaddr & 0x000fffff);
250 ap = (d >> 10) & 3;
251 access = arm_check_access(cpu, ap, dav, user);
252 if (access > writeflag)
253 return access;
254 fs = FAULT_PERM_S;
255 goto exception_return;
256
257 default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x ("
258 "unimplemented type %i)\n", vaddr, d, d&3);
259 exit(1);
260 }
261
262 exception_return:
263 if (no_exceptions)
264 return 0;
265
266 if (!quiet_mode) {
267 fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i "
268 "access=%i user=%i", (int)vaddr, domain, dav, ap,
269 access, user);
270 fatal(" d=0x%08x d2=0x%08x }\n", d, d2);
271 }
272
273 if (instr)
274 arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
275 else {
276 cpu->cd.arm.far = vaddr;
277 cpu->cd.arm.fsr = (domain << 4) | fs;
278 arm_exception(cpu, ARM_EXCEPTION_DATA_ABT);
279 }
280
281 return 0;
282 }
283

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