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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_arm.c,v 1.27 2005/10/23 14:24:13 debug Exp $ |
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* |
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* |
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* TODO/NOTE: The B and/or C bits could also cause the return value to |
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* be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the |
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* translation arrays. TODO: Find out if this is a good thing to do. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "armreg.h" |
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|
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extern int quiet_mode; |
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|
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|
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/* |
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* arm_translate_address(): |
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* |
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* Address translation with the MMU disabled. |
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*/ |
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int arm_translate_address(struct cpu *cpu, uint64_t vaddr64, |
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uint64_t *return_addr, int flags) |
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{ |
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*return_addr = vaddr64 & 0xffffffff; |
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return 2; |
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} |
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|
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|
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/* |
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* arm_check_access(): |
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* |
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* Helper function. Returns 0 for no access, 1 for read-only, and 2 for |
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* read/write. |
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*/ |
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static int arm_check_access(struct cpu *cpu, int ap, int dav, int user) |
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{ |
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int s, r; |
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|
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switch (dav) { |
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case 0: /* No access at all. */ |
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return 0; |
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case 1: /* Normal access check. */ |
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break; |
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case 2: fatal("arm_check_access(): 1 shouldn't be used\n"); |
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exit(1); |
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case 3: /* Anything is allowed. */ |
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return 2; |
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} |
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|
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switch (ap) { |
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case 0: s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0; |
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r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0; |
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switch (s + r) { |
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case 0: return 0; |
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case 1: return user? 0 : 1; |
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case 2: return 1; |
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} |
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fatal("arm_check_access: UNPREDICTABLE s+r value!\n"); |
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return 0; |
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case 1: return user? 0 : 2; |
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case 2: return user? 1 : 2; |
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} |
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|
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/* "case 3": */ |
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return 2; |
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} |
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|
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|
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/* |
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* arm_translate_address_mmu(): |
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* |
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* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
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* |
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* Return values: |
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* 0 Failure |
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* 1 Success, the page is readable only |
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* 2 Success, the page is read/write |
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* |
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* If this is a 1KB page access, then the return value is ORed with |
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* MEMORY_NOT_FULL_PAGE. |
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*/ |
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int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr64, |
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uint64_t *return_addr, int flags) |
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{ |
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unsigned char *q; |
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uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64; |
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int instr = flags & FLAG_INSTR; |
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int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0; |
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int useraccess = flags & MEMORY_USER_ACCESS; |
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int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
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int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32; |
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int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0; |
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int fs = 2; /* fault status (2 = terminal exception) */ |
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int subpage = 0; |
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|
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if (useraccess) |
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user = 1; |
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|
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addr = ((vaddr & 0xfff00000ULL) >> 18); |
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|
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if (cpu->cd.arm.translation_table == NULL || |
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cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) { |
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uint32_t ofs; |
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cpu->cd.arm.translation_table = memory_paddr_to_hostaddr( |
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cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0); |
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if (cpu->cd.arm.translation_table != NULL) { |
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ofs = cpu->cd.arm.ttb & ((1 << BITS_PER_MEMBLOCK) - 1); |
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cpu->cd.arm.translation_table += ofs; |
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} |
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cpu->cd.arm.last_ttb = cpu->cd.arm.ttb; |
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} |
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|
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if (cpu->cd.arm.translation_table != NULL) { |
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d = *(uint32_t *)(cpu->cd.arm.translation_table + addr); |
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#ifdef HOST_LITTLE_ENDIAN |
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if (cpu->byte_order == EMUL_BIG_ENDIAN) |
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#else |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
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#endif |
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d = ((d & 0xff) << 24) | ((d & 0xff00) << 8) | |
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((d & 0xff0000) >> 8) | ((d & 0xff000000) >> 24); |
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} |
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|
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/* Get the domain from the descriptor, and the Domain Access Value: */ |
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domain = (d >> 5) & 15; |
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dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3; |
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|
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switch (d & 3) { |
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|
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case 0: domain = 0; |
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fs = FAULT_TRANS_S; |
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goto exception_return; |
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|
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case 1: /* Course Pagetable: */ |
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if (dav == 0) { |
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fs = FAULT_DOMAIN_P; |
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goto exception_return; |
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} |
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ptba = d & 0xfffffc00; |
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addr = ptba + ((vaddr & 0x000ff000) >> 10); |
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|
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q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0); |
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if (q == NULL) { |
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printf("arm memory blah blah adfh asfg asdgasdg\n"); |
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exit(1); |
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} |
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d2 = *(uint32_t *)(q + (addr & ((1 << BITS_PER_MEMBLOCK) - 1))); |
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#ifdef HOST_LITTLE_ENDIAN |
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if (cpu->byte_order == EMUL_BIG_ENDIAN) |
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#else |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
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#endif |
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d2 = ((d2 & 0xff) << 24) | ((d2 & 0xff00) << 8) | |
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((d2 & 0xff0000) >> 8) | ((d2 & 0xff000000) >> 24); |
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|
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switch (d2 & 3) { |
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case 0: fs = FAULT_TRANS_P; |
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goto exception_return; |
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case 1: /* 16KB page: */ |
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ap = (d2 >> 4) & 255; |
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switch (vaddr & 0x0000c000) { |
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case 0x4000: ap >>= 2; break; |
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case 0x8000: ap >>= 4; break; |
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case 0xc000: ap >>= 6; break; |
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} |
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ap &= 3; |
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*return_addr = (d2 & 0xffff0000) | (vaddr & 0x0000ffff); |
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break; |
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case 2: /* 4KB page: */ |
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ap3 = (d2 >> 10) & 3; |
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ap2 = (d2 >> 8) & 3; |
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ap1 = (d2 >> 6) & 3; |
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ap0 = (d2 >> 4) & 3; |
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switch (vaddr & 0x00000c00) { |
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case 0x000: ap = ap0; break; |
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case 0x400: ap = ap1; break; |
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case 0x800: ap = ap2; break; |
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default: ap = ap3; |
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} |
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if (ap0 != ap1 || ap0 != ap2 || ap0 != ap3) |
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subpage = 1; |
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*return_addr = (d2 & 0xfffff000) | (vaddr & 0x00000fff); |
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break; |
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case 3: /* 1KB page: */ |
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subpage = 1; |
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ap = (d2 >> 4) & 3; |
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*return_addr = (d2 & 0xfffffc00) | (vaddr & 0x000003ff); |
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break; |
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} |
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access = arm_check_access(cpu, ap, dav, user); |
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if (access > writeflag) |
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return access | (subpage? MEMORY_NOT_FULL_PAGE : 0); |
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fs = FAULT_PERM_P; |
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goto exception_return; |
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|
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case 2: /* Section descriptor: */ |
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if (dav == 0) { |
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fs = FAULT_DOMAIN_S; |
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goto exception_return; |
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} |
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*return_addr = (d & 0xfff00000) | (vaddr & 0x000fffff); |
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ap = (d >> 10) & 3; |
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access = arm_check_access(cpu, ap, dav, user); |
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if (access > writeflag) |
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return access; |
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fs = FAULT_PERM_S; |
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goto exception_return; |
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|
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default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x (" |
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"unimplemented type %i)\n", vaddr, d, d&3); |
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exit(1); |
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} |
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|
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exception_return: |
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if (no_exceptions) |
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return 0; |
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|
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if (!quiet_mode) { |
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fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i " |
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"access=%i user=%i", (int)vaddr, domain, dav, ap, |
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access, user); |
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fatal(" d=0x%08x d2=0x%08x }\n", d, d2); |
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} |
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|
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if (instr) |
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arm_exception(cpu, ARM_EXCEPTION_PREF_ABT); |
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else { |
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cpu->cd.arm.far = vaddr; |
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cpu->cd.arm.fsr = (domain << 4) | fs; |
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arm_exception(cpu, ARM_EXCEPTION_DATA_ABT); |
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} |
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|
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return 0; |
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} |
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