1 |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
3 |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
6 |
* |
7 |
* 1. Redistributions of source code must retain the above copyright |
8 |
* notice, this list of conditions and the following disclaimer. |
9 |
* 2. Redistributions in binary form must reproduce the above copyright |
10 |
* notice, this list of conditions and the following disclaimer in the |
11 |
* documentation and/or other materials provided with the distribution. |
12 |
* 3. The name of the author may not be used to endorse or promote products |
13 |
* derived from this software without specific prior written permission. |
14 |
* |
15 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
16 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
18 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
19 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
20 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
21 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
22 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
23 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
25 |
* SUCH DAMAGE. |
26 |
* |
27 |
* |
28 |
* $Id: memory_arm.c,v 1.23 2005/10/07 15:19:48 debug Exp $ |
29 |
* |
30 |
* |
31 |
* TODO/NOTE: There are probably two solutions to the subpage access |
32 |
* permission problem: |
33 |
* |
34 |
* a) the obvious (almost trivial) solution is to decrease the native page |
35 |
* size from 4 KB to 1 KB. That would ruin the rest of the translation |
36 |
* system though. (It would be infeasible to hold the entire address |
37 |
* space in 1-level tables.) |
38 |
* |
39 |
* b) to return something else than just 0, 1, or 2 from arm_memory_rw(). |
40 |
* Perhaps |4, which would indicate that the vaddr => paddr conversion |
41 |
* was done, but that it should not be entered into the cache. This could |
42 |
* also be used in combination with the B and C bits (which are currently |
43 |
* ignored). |
44 |
* |
45 |
* b would probably be the best solution. |
46 |
*/ |
47 |
|
48 |
#include <stdio.h> |
49 |
#include <stdlib.h> |
50 |
#include <string.h> |
51 |
|
52 |
#include "cpu.h" |
53 |
#include "memory.h" |
54 |
#include "misc.h" |
55 |
|
56 |
#include "armreg.h" |
57 |
|
58 |
extern int quiet_mode; |
59 |
|
60 |
|
61 |
/* |
62 |
* arm_check_access(): |
63 |
* |
64 |
* Helper function. Returns 0 for no access, 1 for read-only, and 2 for |
65 |
* read/write. |
66 |
*/ |
67 |
static int arm_check_access(struct cpu *cpu, int ap, int dav, int user) |
68 |
{ |
69 |
int s, r; |
70 |
|
71 |
switch (dav) { |
72 |
case 0: /* No access at all. */ |
73 |
return 0; |
74 |
case 1: /* Normal access check. */ |
75 |
break; |
76 |
case 2: fatal("arm_check_access(): 1 shouldn't be used\n"); |
77 |
exit(1); |
78 |
case 3: /* Anything is allowed. */ |
79 |
return 2; |
80 |
} |
81 |
|
82 |
switch (ap) { |
83 |
case 0: s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0; |
84 |
r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0; |
85 |
switch (s + r) { |
86 |
case 0: return 0; |
87 |
case 1: return user? 0 : 1; |
88 |
case 2: return 1; |
89 |
} |
90 |
fatal("arm_check_access: UNPREDICTABLE s+r value!\n"); |
91 |
return 0; |
92 |
case 1: return user? 0 : 2; |
93 |
case 2: return user? 1 : 2; |
94 |
} |
95 |
|
96 |
/* "case 3": */ |
97 |
return 2; |
98 |
} |
99 |
|
100 |
|
101 |
/* |
102 |
* arm_translate_address(): |
103 |
* |
104 |
* Don't call this function is userland_emul is non-NULL, or cpu is NULL. |
105 |
* |
106 |
* Return values: |
107 |
* 0 Failure |
108 |
* 1 Success, the page is readable only |
109 |
* 2 Success, the page is read/write |
110 |
*/ |
111 |
int arm_translate_address(struct cpu *cpu, uint64_t vaddr64, |
112 |
uint64_t *return_addr, int flags) |
113 |
{ |
114 |
unsigned char descr[4]; |
115 |
uint32_t addr, d, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64; |
116 |
int d2_in_use = 0, d_in_use = 1; |
117 |
int instr = flags & FLAG_INSTR; |
118 |
int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0; |
119 |
int useraccess = flags & MEMORY_USER_ACCESS; |
120 |
int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
121 |
int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32; |
122 |
int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0; |
123 |
int fs = 2; /* fault status (2 = terminal exception) */ |
124 |
|
125 |
if (!(cpu->cd.arm.control & ARM_CONTROL_MMU)) { |
126 |
*return_addr = vaddr; |
127 |
return 2; |
128 |
} |
129 |
|
130 |
if (useraccess) |
131 |
user = 1; |
132 |
|
133 |
addr = cpu->cd.arm.ttb + ((vaddr & 0xfff00000ULL) >> 18); |
134 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, &descr[0], |
135 |
sizeof(descr), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) { |
136 |
fatal("arm_translate_address(): huh?\n"); |
137 |
exit(1); |
138 |
} |
139 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
140 |
d = descr[0] + (descr[1] << 8) + (descr[2] << 16) |
141 |
+ (descr[3] << 24); |
142 |
else |
143 |
d = descr[3] + (descr[2] << 8) + (descr[1] << 16) |
144 |
+ (descr[0] << 24); |
145 |
|
146 |
/* fatal("vaddr=0x%08x ttb=0x%08x addr=0x%08x d=0x%08x\n", |
147 |
vaddr, cpu->cd.arm.ttb, addr, d); */ |
148 |
|
149 |
/* Get the domain from the descriptor, and the Domain Access Value: */ |
150 |
domain = (d >> 5) & 15; |
151 |
dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3; |
152 |
|
153 |
switch (d & 3) { |
154 |
|
155 |
case 0: d_in_use = 0; |
156 |
domain = 0; |
157 |
fs = FAULT_TRANS_S; |
158 |
goto exception_return; |
159 |
|
160 |
case 1: /* Course Pagetable: */ |
161 |
ptba = d & 0xfffffc00; |
162 |
addr = ptba + ((vaddr & 0x000ff000) >> 10); |
163 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, &descr[0], |
164 |
sizeof(descr), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) { |
165 |
fatal("arm_translate_address(): huh 2?\n"); |
166 |
exit(1); |
167 |
} |
168 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
169 |
d2 = descr[0] + (descr[1] << 8) + (descr[2] << 16) |
170 |
+ (descr[3] << 24); |
171 |
else |
172 |
d2 = descr[3] + (descr[2] << 8) + (descr[1] << 16) |
173 |
+ (descr[0] << 24); |
174 |
d2_in_use = 1; |
175 |
|
176 |
switch (d2 & 3) { |
177 |
case 0: fs = FAULT_TRANS_P; |
178 |
goto exception_return; |
179 |
case 1: /* 16KB page: */ |
180 |
ap = (d2 >> 4) & 255; |
181 |
switch (vaddr & 0x0000c000) { |
182 |
case 0x4000: ap >>= 2; break; |
183 |
case 0x8000: ap >>= 4; break; |
184 |
case 0xc000: ap >>= 6; break; |
185 |
} |
186 |
ap &= 3; |
187 |
*return_addr = (d2 & 0xffff0000) | (vaddr & 0x0000ffff); |
188 |
break; |
189 |
case 2: /* 4KB page: */ |
190 |
ap3 = (d2 >> 10) & 3; |
191 |
ap2 = (d2 >> 8) & 3; |
192 |
ap1 = (d2 >> 6) & 3; |
193 |
ap0 = (d2 >> 4) & 3; |
194 |
switch (vaddr & 0x00000c00) { |
195 |
case 0x000: ap = ap0; break; |
196 |
case 0x400: ap = ap1; break; |
197 |
case 0x800: ap = ap2; break; |
198 |
default: ap = ap3; |
199 |
} |
200 |
#if 0 |
201 |
if ((ap0 != ap1 || ap0 != ap2 || ap0 != ap3) && |
202 |
!no_exceptions) |
203 |
fatal("WARNING: vaddr = 0x%08x, small page, but" |
204 |
" different access permissions for the sub" |
205 |
"pages! This is not really implemented " |
206 |
"yet.\n", (int)vaddr); |
207 |
#endif |
208 |
*return_addr = (d2 & 0xfffff000) | (vaddr & 0x00000fff); |
209 |
break; |
210 |
case 3: /* 1KB page: */ |
211 |
fatal("WARNING: 1 KB page! Not implemented yet.\n"); |
212 |
ap = (d2 >> 4) & 3; |
213 |
*return_addr = (d2 & 0xfffffc00) | (vaddr & 0x000003ff); |
214 |
break; |
215 |
} |
216 |
if (dav == 0) { |
217 |
fs = FAULT_DOMAIN_P; |
218 |
goto exception_return; |
219 |
} |
220 |
access = arm_check_access(cpu, ap, dav, user); |
221 |
if (access > writeflag) |
222 |
return access; |
223 |
fs = FAULT_PERM_P; |
224 |
goto exception_return; |
225 |
|
226 |
case 2: /* Section descriptor: */ |
227 |
*return_addr = (d & 0xfff00000) | (vaddr & 0x000fffff); |
228 |
if (dav == 0) { |
229 |
fs = FAULT_DOMAIN_S; |
230 |
goto exception_return; |
231 |
} |
232 |
ap = (d >> 10) & 3; |
233 |
access = arm_check_access(cpu, ap, dav, user); |
234 |
if (access > writeflag) |
235 |
return access; |
236 |
fs = FAULT_PERM_S; |
237 |
goto exception_return; |
238 |
|
239 |
default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x (" |
240 |
"unimplemented type %i)\n", vaddr, d, d&3); |
241 |
exit(1); |
242 |
} |
243 |
|
244 |
exception_return: |
245 |
if (no_exceptions) |
246 |
return 0; |
247 |
|
248 |
if (!quiet_mode) { |
249 |
fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i " |
250 |
"access=%i user=%i", (int)vaddr, domain, dav, ap, |
251 |
access, user); |
252 |
if (d_in_use) |
253 |
fatal(" d=0x%08x", d); |
254 |
if (d2_in_use) |
255 |
fatal(" d2=0x%08x", d2); |
256 |
fatal(" }\n"); |
257 |
} |
258 |
|
259 |
if (instr) |
260 |
arm_exception(cpu, ARM_EXCEPTION_PREF_ABT); |
261 |
else { |
262 |
cpu->cd.arm.far = vaddr; |
263 |
cpu->cd.arm.fsr = (domain << 4) | fs; |
264 |
arm_exception(cpu, ARM_EXCEPTION_DATA_ABT); |
265 |
} |
266 |
|
267 |
return 0; |
268 |
} |
269 |
|