src/cpus/memory_arm.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: memory_arm.c,v 1.33 2006/01/25 05:51:12 debug Exp $
 *
 *
 *  TODO/NOTE:  The B and/or C bits could also cause the return value to
 *  be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the
 *  translation arrays. TODO: Find out if this is a good thing to do.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "arm_cpu_types.h"
#include "cpu.h"
#include "memory.h"
#include "misc.h"

#include "armreg.h"

extern int quiet_mode;


/*
 *  arm_translate_address():
 *
 *  Address translation with the MMU disabled.
 */
int arm_translate_address(struct cpu *cpu, uint64_t vaddr64,
        uint64_t *return_addr, int flags)
{
        *return_addr = vaddr64 & 0xffffffff;
        return 2;
}


/*
 *  arm_check_access():
 *
 *  Helper function.  Returns 0 for no access, 1 for read-only, and 2 for
 *  read/write.
 */
static int arm_check_access(struct cpu *cpu, int ap, int dav, int user)
{
        int s, r;

        switch (dav) {
        case 0: /*  No access at all.  */
                return 0;
        case 1: /*  Normal access check.  */
                break;
        case 2: fatal("arm_check_access(): 1 shouldn't be used\n");
                exit(1);
        case 3: /*  Anything is allowed.  */
                return 2;
        }

        switch (ap) {
        case 0: s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0;
                r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0;
                switch (s + r) {
                case 0: return 0;
                case 1: return user? 0 : 1;
                case 2: return 1;
                }
                fatal("arm_check_access: UNPREDICTABLE s+r value!\n");
                return 0;
        case 1: return user? 0 : 2;
        case 2: return user? 1 : 2;
        }

        /*  "case 3":  */
        return 2;
}


/*
 *  arm_translate_address_mmu():
 *
 *  Don't call this function is userland_emul is non-NULL, or cpu is NULL.
 *
 *  Return values:
 *      0  Failure
 *      1  Success, the page is readable only
 *      2  Success, the page is read/write
 *
 *  If this is a 1KB page access, then the return value is ORed with
 *  MEMORY_NOT_FULL_PAGE.
 */
int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr64,
        uint64_t *return_addr, int flags)
{
        unsigned char *q;
        uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64;
        int instr = flags & FLAG_INSTR;
        int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
        int useraccess = flags & MEMORY_USER_ACCESS;
        int no_exceptions = flags & FLAG_NOEXCEPTIONS;
        int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32;
        int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0;
        int fs = 2;             /*  fault status (2 = terminal exception)  */
        int subpage = 0;

        if (useraccess)
                user = 1;

        addr = ((vaddr & 0xfff00000ULL) >> 18);

        if (cpu->cd.arm.translation_table == NULL ||
            cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) {
                uint32_t ofs;
                cpu->cd.arm.translation_table = memory_paddr_to_hostaddr(
                    cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0);
                if (cpu->cd.arm.translation_table != NULL) {
                        ofs = cpu->cd.arm.ttb & ((1 << BITS_PER_MEMBLOCK) - 1);
                        cpu->cd.arm.translation_table += ofs;
                }
                cpu->cd.arm.last_ttb = cpu->cd.arm.ttb;
        }

        if (cpu->cd.arm.translation_table != NULL) {
                d = *(uint32_t *)(cpu->cd.arm.translation_table + addr);
#ifdef HOST_LITTLE_ENDIAN
                if (cpu->byte_order == EMUL_BIG_ENDIAN)
#else
                if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
#endif
                        d = ((d & 0xff) << 24) | ((d & 0xff00) << 8) |
                            ((d & 0xff0000) >> 8) | ((d & 0xff000000) >> 24);
        }

        /*  Get the domain from the descriptor, and the Domain Access Value:  */
        domain = (d >> 5) & 15;
        dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3;

        switch (d & 3) {

        case 0: domain = 0;
                fs = FAULT_TRANS_S;
                goto exception_return;

        case 1: /*  Course Pagetable:  */
                if (dav == 0) {
                        fs = FAULT_DOMAIN_P;
                        goto exception_return;
                }
                ptba = d & 0xfffffc00;
                addr = ptba + ((vaddr & 0x000ff000) >> 10);

                q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0);
                if (q == NULL) {
                        printf("arm memory blah blah adfh asfg asdgasdg\n");
                        exit(1);
                }
                d2 = *(uint32_t *)(q + (addr & ((1 << BITS_PER_MEMBLOCK) - 1)));
#ifdef HOST_LITTLE_ENDIAN
                if (cpu->byte_order == EMUL_BIG_ENDIAN)
#else
                if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
#endif
                        d2 = ((d2 & 0xff) << 24) | ((d2 & 0xff00) << 8) |
                             ((d2 & 0xff0000) >> 8) | ((d2 & 0xff000000) >> 24);

                switch (d2 & 3) {
                case 0: fs = FAULT_TRANS_P;
                        goto exception_return;
                case 1: /*  16KB page:  */
                        ap = (d2 >> 4) & 255;
                        switch (vaddr & 0x0000c000) {
                        case 0x4000:    ap >>= 2; break;
                        case 0x8000:    ap >>= 4; break;
                        case 0xc000:    ap >>= 6; break;
                        }
                        ap &= 3;
                        *return_addr = (d2 & 0xffff0000) | (vaddr & 0x0000ffff);
                        break;
                case 3: if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
                                /*  4KB page (Xscale)  */
                                subpage = 0;
                        } else {
                                /*  1KB page  */
                                subpage = 1;
                                ap = (d2 >> 4) & 3;
                                *return_addr = (d2 & 0xfffffc00) |
                                    (vaddr & 0x000003ff);
                                break;
                        }
                        /*  NOTE: Fall-through for XScale!  */
                case 2: /*  4KB page:  */
                        ap3 = (d2 >> 10) & 3;
                        ap2 = (d2 >>  8) & 3;
                        ap1 = (d2 >>  6) & 3;
                        ap0 = (d2 >>  4) & 3;
                        switch (vaddr & 0x00000c00) {
                        case 0x000: ap = ap0; break;
                        case 0x400: ap = ap1; break;
                        case 0x800: ap = ap2; break;
                        default:    ap = ap3;
                        }
                        /*  NOTE: Ugly hack for XScale:  */
                        if ((d2 & 3) == 3) {
                                /*  Treated as 4KB page:  */
                                ap = ap0;
                        } else {
                                if (ap0 != ap1 || ap0 != ap2 || ap0 != ap3)
                                        subpage = 1;
                        }
                        *return_addr = (d2 & 0xfffff000) | (vaddr & 0x00000fff);
                        break;
                }
                access = arm_check_access(cpu, ap, dav, user);
                if (access > writeflag)
                        return access | (subpage? MEMORY_NOT_FULL_PAGE : 0);
                fs = FAULT_PERM_P;
                goto exception_return;

        case 2: /*  Section descriptor:  */
                if (dav == 0) {
                        fs = FAULT_DOMAIN_S;
                        goto exception_return;
                }
                *return_addr = (d & 0xfff00000) | (vaddr & 0x000fffff);
                ap = (d >> 10) & 3;
                access = arm_check_access(cpu, ap, dav, user);
                if (access > writeflag)
                        return access;
                fs = FAULT_PERM_S;
                goto exception_return;

        default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x ("
                    "unimplemented type %i)\n", vaddr, d, d&3);
                exit(1);
        }

exception_return:
        if (no_exceptions)
                return 0;

        if (!quiet_mode) {
                fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i "
                    "access=%i user=%i", (int)vaddr, domain, dav, ap,
                    access, user);
                fatal(" d=0x%08x d2=0x%08x pc=0x%08x }\n", d, d2, (int)cpu->pc);
        }

        if (instr)
                arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
        else {
                cpu->cd.arm.far = vaddr;
                cpu->cd.arm.fsr = (domain << 4) | fs;
                arm_exception(cpu, ARM_EXCEPTION_DATA_ABT);
        }

        return 0;
}

1	dpavlin	14	/*
2			* Copyright (C) 2005 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	22	* $Id: memory_arm.c,v 1.33 2006/01/25 05:51:12 debug Exp $
29	dpavlin	14	*
30			*
31	dpavlin	18	* TODO/NOTE: The B and/or C bits could also cause the return value to
32			* be MEMORY_NOT_FULL_PAGE, to make sure it doesn't get entered into the
33			* translation arrays. TODO: Find out if this is a good thing to do.
34	dpavlin	14	*/
35
36			#include <stdio.h>
37			#include <stdlib.h>
38			#include <string.h>
39
40	dpavlin	22	#include "arm_cpu_types.h"
41	dpavlin	14	#include "cpu.h"
42			#include "memory.h"
43			#include "misc.h"
44
45			#include "armreg.h"
46
47			extern int quiet_mode;
48
49
50			/*
51	dpavlin	18	* arm_translate_address():
52			*
53			* Address translation with the MMU disabled.
54			*/
55			int arm_translate_address(struct cpu *cpu, uint64_t vaddr64,
56			uint64_t *return_addr, int flags)
57			{
58			*return_addr = vaddr64 & 0xffffffff;
59			return 2;
60			}
61
62
63			/*
64	dpavlin	14	* arm_check_access():
65			*
66			* Helper function. Returns 0 for no access, 1 for read-only, and 2 for
67			* read/write.
68			*/
69			static int arm_check_access(struct cpu *cpu, int ap, int dav, int user)
70			{
71			int s, r;
72
73			switch (dav) {
74			case 0: /* No access at all. */
75			return 0;
76			case 1: /* Normal access check. */
77			break;
78			case 2: fatal("arm_check_access(): 1 shouldn't be used\n");
79			exit(1);
80			case 3: /* Anything is allowed. */
81			return 2;
82			}
83
84			switch (ap) {
85			case 0: s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0;
86			r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0;
87			switch (s + r) {
88			case 0: return 0;
89			case 1: return user? 0 : 1;
90			case 2: return 1;
91			}
92			fatal("arm_check_access: UNPREDICTABLE s+r value!\n");
93			return 0;
94			case 1: return user? 0 : 2;
95			case 2: return user? 1 : 2;
96			}
97
98			/* "case 3": */
99			return 2;
100			}
101
102
103			/*
104	dpavlin	18	* arm_translate_address_mmu():
105	dpavlin	14	*
106			* Don't call this function is userland_emul is non-NULL, or cpu is NULL.
107			*
108			* Return values:
109			* 0 Failure
110			* 1 Success, the page is readable only
111			* 2 Success, the page is read/write
112	dpavlin	18	*
113			* If this is a 1KB page access, then the return value is ORed with
114			* MEMORY_NOT_FULL_PAGE.
115	dpavlin	14	*/
116	dpavlin	18	int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr64,
117	dpavlin	14	uint64_t *return_addr, int flags)
118			{
119	dpavlin	18	unsigned char *q;
120			uint32_t addr, d=0, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64;
121	dpavlin	14	int instr = flags & FLAG_INSTR;
122			int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
123			int useraccess = flags & MEMORY_USER_ACCESS;
124			int no_exceptions = flags & FLAG_NOEXCEPTIONS;
125			int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32;
126			int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0;
127			int fs = 2; /* fault status (2 = terminal exception) */
128	dpavlin	18	int subpage = 0;
129	dpavlin	14
130			if (useraccess)
131			user = 1;
132
133	dpavlin	18	addr = ((vaddr & 0xfff00000ULL) >> 18);
134
135			if (cpu->cd.arm.translation_table == NULL \|\|
136			cpu->cd.arm.ttb != cpu->cd.arm.last_ttb) {
137			uint32_t ofs;
138			cpu->cd.arm.translation_table = memory_paddr_to_hostaddr(
139			cpu->mem, cpu->cd.arm.ttb & 0x0fffffff, 0);
140			if (cpu->cd.arm.translation_table != NULL) {
141			ofs = cpu->cd.arm.ttb & ((1 << BITS_PER_MEMBLOCK) - 1);
142			cpu->cd.arm.translation_table += ofs;
143			}
144			cpu->cd.arm.last_ttb = cpu->cd.arm.ttb;
145	dpavlin	14	}
146
147	dpavlin	18	if (cpu->cd.arm.translation_table != NULL) {
148			d = (uint32_t )(cpu->cd.arm.translation_table + addr);
149			#ifdef HOST_LITTLE_ENDIAN
150			if (cpu->byte_order == EMUL_BIG_ENDIAN)
151			#else
152			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
153			#endif
154			d = ((d & 0xff) << 24) \| ((d & 0xff00) << 8) \|
155			((d & 0xff0000) >> 8) \| ((d & 0xff000000) >> 24);
156			}
157	dpavlin	14
158			/* Get the domain from the descriptor, and the Domain Access Value: */
159			domain = (d >> 5) & 15;
160			dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3;
161
162			switch (d & 3) {
163
164	dpavlin	18	case 0: domain = 0;
165	dpavlin	14	fs = FAULT_TRANS_S;
166			goto exception_return;
167
168			case 1: /* Course Pagetable: */
169	dpavlin	18	if (dav == 0) {
170			fs = FAULT_DOMAIN_P;
171			goto exception_return;
172			}
173	dpavlin	14	ptba = d & 0xfffffc00;
174			addr = ptba + ((vaddr & 0x000ff000) >> 10);
175	dpavlin	18
176			q = memory_paddr_to_hostaddr(cpu->mem, addr & 0x0fffffff, 0);
177			if (q == NULL) {
178			printf("arm memory blah blah adfh asfg asdgasdg\n");
179	dpavlin	14	exit(1);
180			}
181	dpavlin	18	d2 = (uint32_t )(q + (addr & ((1 << BITS_PER_MEMBLOCK) - 1)));
182			#ifdef HOST_LITTLE_ENDIAN
183			if (cpu->byte_order == EMUL_BIG_ENDIAN)
184			#else
185	dpavlin	14	if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
186	dpavlin	18	#endif
187			d2 = ((d2 & 0xff) << 24) \| ((d2 & 0xff00) << 8) \|
188			((d2 & 0xff0000) >> 8) \| ((d2 & 0xff000000) >> 24);
189	dpavlin	14
190			switch (d2 & 3) {
191			case 0: fs = FAULT_TRANS_P;
192			goto exception_return;
193			case 1: /* 16KB page: */
194			ap = (d2 >> 4) & 255;
195			switch (vaddr & 0x0000c000) {
196			case 0x4000: ap >>= 2; break;
197			case 0x8000: ap >>= 4; break;
198			case 0xc000: ap >>= 6; break;
199			}
200			ap &= 3;
201			*return_addr = (d2 & 0xffff0000) \| (vaddr & 0x0000ffff);
202			break;
203	dpavlin	22	case 3: if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
204			/* 4KB page (Xscale) */
205			subpage = 0;
206			} else {
207			/* 1KB page */
208			subpage = 1;
209			ap = (d2 >> 4) & 3;
210			*return_addr = (d2 & 0xfffffc00) \|
211			(vaddr & 0x000003ff);
212			break;
213	dpavlin	20	}
214	dpavlin	22	/* NOTE: Fall-through for XScale! */
215	dpavlin	14	case 2: /* 4KB page: */
216			ap3 = (d2 >> 10) & 3;
217			ap2 = (d2 >> 8) & 3;
218			ap1 = (d2 >> 6) & 3;
219			ap0 = (d2 >> 4) & 3;
220			switch (vaddr & 0x00000c00) {
221			case 0x000: ap = ap0; break;
222			case 0x400: ap = ap1; break;
223			case 0x800: ap = ap2; break;
224			default: ap = ap3;
225			}
226	dpavlin	22	/* NOTE: Ugly hack for XScale: */
227			if ((d2 & 3) == 3) {
228			/* Treated as 4KB page: */
229	dpavlin	20	ap = ap0;
230	dpavlin	22	} else {
231			if (ap0 != ap1 \|\| ap0 != ap2 \|\| ap0 != ap3)
232			subpage = 1;
233			}
234	dpavlin	14	*return_addr = (d2 & 0xfffff000) \| (vaddr & 0x00000fff);
235			break;
236			}
237			access = arm_check_access(cpu, ap, dav, user);
238			if (access > writeflag)
239	dpavlin	18	return access \| (subpage? MEMORY_NOT_FULL_PAGE : 0);
240	dpavlin	14	fs = FAULT_PERM_P;
241			goto exception_return;
242
243			case 2: /* Section descriptor: */
244			if (dav == 0) {
245			fs = FAULT_DOMAIN_S;
246			goto exception_return;
247			}
248	dpavlin	18	*return_addr = (d & 0xfff00000) \| (vaddr & 0x000fffff);
249	dpavlin	14	ap = (d >> 10) & 3;
250			access = arm_check_access(cpu, ap, dav, user);
251			if (access > writeflag)
252			return access;
253			fs = FAULT_PERM_S;
254			goto exception_return;
255
256			default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x ("
257			"unimplemented type %i)\n", vaddr, d, d&3);
258			exit(1);
259			}
260
261			exception_return:
262			if (no_exceptions)
263			return 0;
264
265			if (!quiet_mode) {
266			fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i "
267			"access=%i user=%i", (int)vaddr, domain, dav, ap,
268			access, user);
269	dpavlin	22	fatal(" d=0x%08x d2=0x%08x pc=0x%08x }\n", d, d2, (int)cpu->pc);
270	dpavlin	14	}
271
272			if (instr)
273			arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
274			else {
275			cpu->cd.arm.far = vaddr;
276			cpu->cd.arm.fsr = (domain << 4) \| fs;
277			arm_exception(cpu, ARM_EXCEPTION_DATA_ABT);
278			}
279
280			return 0;
281			}
282