/[gxemul]/trunk/src/cpus/memory_arm.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/memory_arm.c

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Revision 14 - (hide annotations)
Mon Oct 8 16:18:51 2007 UTC (14 years, 2 months ago) by dpavlin
File MIME type: text/plain
File size: 7912 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 dpavlin 14 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28     * $Id: memory_arm.c,v 1.23 2005/10/07 15:19:48 debug Exp $
29     *
30     *
31     * TODO/NOTE: There are probably two solutions to the subpage access
32     * permission problem:
33     *
34     * a) the obvious (almost trivial) solution is to decrease the native page
35     * size from 4 KB to 1 KB. That would ruin the rest of the translation
36     * system though. (It would be infeasible to hold the entire address
37     * space in 1-level tables.)
38     *
39     * b) to return something else than just 0, 1, or 2 from arm_memory_rw().
40     * Perhaps |4, which would indicate that the vaddr => paddr conversion
41     * was done, but that it should not be entered into the cache. This could
42     * also be used in combination with the B and C bits (which are currently
43     * ignored).
44     *
45     * b would probably be the best solution.
46     */
47    
48     #include <stdio.h>
49     #include <stdlib.h>
50     #include <string.h>
51    
52     #include "cpu.h"
53     #include "memory.h"
54     #include "misc.h"
55    
56     #include "armreg.h"
57    
58     extern int quiet_mode;
59    
60    
61     /*
62     * arm_check_access():
63     *
64     * Helper function. Returns 0 for no access, 1 for read-only, and 2 for
65     * read/write.
66     */
67     static int arm_check_access(struct cpu *cpu, int ap, int dav, int user)
68     {
69     int s, r;
70    
71     switch (dav) {
72     case 0: /* No access at all. */
73     return 0;
74     case 1: /* Normal access check. */
75     break;
76     case 2: fatal("arm_check_access(): 1 shouldn't be used\n");
77     exit(1);
78     case 3: /* Anything is allowed. */
79     return 2;
80     }
81    
82     switch (ap) {
83     case 0: s = (cpu->cd.arm.control & ARM_CONTROL_S)? 1 : 0;
84     r = (cpu->cd.arm.control & ARM_CONTROL_R)? 2 : 0;
85     switch (s + r) {
86     case 0: return 0;
87     case 1: return user? 0 : 1;
88     case 2: return 1;
89     }
90     fatal("arm_check_access: UNPREDICTABLE s+r value!\n");
91     return 0;
92     case 1: return user? 0 : 2;
93     case 2: return user? 1 : 2;
94     }
95    
96     /* "case 3": */
97     return 2;
98     }
99    
100    
101     /*
102     * arm_translate_address():
103     *
104     * Don't call this function is userland_emul is non-NULL, or cpu is NULL.
105     *
106     * Return values:
107     * 0 Failure
108     * 1 Success, the page is readable only
109     * 2 Success, the page is read/write
110     */
111     int arm_translate_address(struct cpu *cpu, uint64_t vaddr64,
112     uint64_t *return_addr, int flags)
113     {
114     unsigned char descr[4];
115     uint32_t addr, d, d2 = (uint32_t)(int32_t)-1, ptba, vaddr = vaddr64;
116     int d2_in_use = 0, d_in_use = 1;
117     int instr = flags & FLAG_INSTR;
118     int writeflag = (flags & FLAG_WRITEFLAG)? 1 : 0;
119     int useraccess = flags & MEMORY_USER_ACCESS;
120     int no_exceptions = flags & FLAG_NOEXCEPTIONS;
121     int user = (cpu->cd.arm.cpsr & ARM_FLAG_MODE) == ARM_MODE_USR32;
122     int domain, dav, ap0,ap1,ap2,ap3, ap = 0, access = 0;
123     int fs = 2; /* fault status (2 = terminal exception) */
124    
125     if (!(cpu->cd.arm.control & ARM_CONTROL_MMU)) {
126     *return_addr = vaddr;
127     return 2;
128     }
129    
130     if (useraccess)
131     user = 1;
132    
133     addr = cpu->cd.arm.ttb + ((vaddr & 0xfff00000ULL) >> 18);
134     if (!cpu->memory_rw(cpu, cpu->mem, addr, &descr[0],
135     sizeof(descr), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
136     fatal("arm_translate_address(): huh?\n");
137     exit(1);
138     }
139     if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
140     d = descr[0] + (descr[1] << 8) + (descr[2] << 16)
141     + (descr[3] << 24);
142     else
143     d = descr[3] + (descr[2] << 8) + (descr[1] << 16)
144     + (descr[0] << 24);
145    
146     /* fatal("vaddr=0x%08x ttb=0x%08x addr=0x%08x d=0x%08x\n",
147     vaddr, cpu->cd.arm.ttb, addr, d); */
148    
149     /* Get the domain from the descriptor, and the Domain Access Value: */
150     domain = (d >> 5) & 15;
151     dav = (cpu->cd.arm.dacr >> (domain * 2)) & 3;
152    
153     switch (d & 3) {
154    
155     case 0: d_in_use = 0;
156     domain = 0;
157     fs = FAULT_TRANS_S;
158     goto exception_return;
159    
160     case 1: /* Course Pagetable: */
161     ptba = d & 0xfffffc00;
162     addr = ptba + ((vaddr & 0x000ff000) >> 10);
163     if (!cpu->memory_rw(cpu, cpu->mem, addr, &descr[0],
164     sizeof(descr), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
165     fatal("arm_translate_address(): huh 2?\n");
166     exit(1);
167     }
168     if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
169     d2 = descr[0] + (descr[1] << 8) + (descr[2] << 16)
170     + (descr[3] << 24);
171     else
172     d2 = descr[3] + (descr[2] << 8) + (descr[1] << 16)
173     + (descr[0] << 24);
174     d2_in_use = 1;
175    
176     switch (d2 & 3) {
177     case 0: fs = FAULT_TRANS_P;
178     goto exception_return;
179     case 1: /* 16KB page: */
180     ap = (d2 >> 4) & 255;
181     switch (vaddr & 0x0000c000) {
182     case 0x4000: ap >>= 2; break;
183     case 0x8000: ap >>= 4; break;
184     case 0xc000: ap >>= 6; break;
185     }
186     ap &= 3;
187     *return_addr = (d2 & 0xffff0000) | (vaddr & 0x0000ffff);
188     break;
189     case 2: /* 4KB page: */
190     ap3 = (d2 >> 10) & 3;
191     ap2 = (d2 >> 8) & 3;
192     ap1 = (d2 >> 6) & 3;
193     ap0 = (d2 >> 4) & 3;
194     switch (vaddr & 0x00000c00) {
195     case 0x000: ap = ap0; break;
196     case 0x400: ap = ap1; break;
197     case 0x800: ap = ap2; break;
198     default: ap = ap3;
199     }
200     #if 0
201     if ((ap0 != ap1 || ap0 != ap2 || ap0 != ap3) &&
202     !no_exceptions)
203     fatal("WARNING: vaddr = 0x%08x, small page, but"
204     " different access permissions for the sub"
205     "pages! This is not really implemented "
206     "yet.\n", (int)vaddr);
207     #endif
208     *return_addr = (d2 & 0xfffff000) | (vaddr & 0x00000fff);
209     break;
210     case 3: /* 1KB page: */
211     fatal("WARNING: 1 KB page! Not implemented yet.\n");
212     ap = (d2 >> 4) & 3;
213     *return_addr = (d2 & 0xfffffc00) | (vaddr & 0x000003ff);
214     break;
215     }
216     if (dav == 0) {
217     fs = FAULT_DOMAIN_P;
218     goto exception_return;
219     }
220     access = arm_check_access(cpu, ap, dav, user);
221     if (access > writeflag)
222     return access;
223     fs = FAULT_PERM_P;
224     goto exception_return;
225    
226     case 2: /* Section descriptor: */
227     *return_addr = (d & 0xfff00000) | (vaddr & 0x000fffff);
228     if (dav == 0) {
229     fs = FAULT_DOMAIN_S;
230     goto exception_return;
231     }
232     ap = (d >> 10) & 3;
233     access = arm_check_access(cpu, ap, dav, user);
234     if (access > writeflag)
235     return access;
236     fs = FAULT_PERM_S;
237     goto exception_return;
238    
239     default:fatal("TODO: descriptor for vaddr 0x%08x: 0x%08x ("
240     "unimplemented type %i)\n", vaddr, d, d&3);
241     exit(1);
242     }
243    
244     exception_return:
245     if (no_exceptions)
246     return 0;
247    
248     if (!quiet_mode) {
249     fatal("{ arm memory fault: vaddr=0x%08x domain=%i dav=%i ap=%i "
250     "access=%i user=%i", (int)vaddr, domain, dav, ap,
251     access, user);
252     if (d_in_use)
253     fatal(" d=0x%08x", d);
254     if (d2_in_use)
255     fatal(" d2=0x%08x", d2);
256     fatal(" }\n");
257     }
258    
259     if (instr)
260     arm_exception(cpu, ARM_EXCEPTION_PREF_ABT);
261     else {
262     cpu->cd.arm.far = vaddr;
263     cpu->cd.arm.fsr = (domain << 4) | fs;
264     arm_exception(cpu, ARM_EXCEPTION_DATA_ABT);
265     }
266    
267     return 0;
268     }
269    

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