/[gxemul]/trunk/src/cpus/generate_tail.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/generate_tail.c

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Revision 14 - (hide annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 7170 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 dpavlin 14 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28     * $Id: generate_tail.c,v 1.5 2005/09/18 19:54:14 debug Exp $
29     */
30    
31     #include <stdio.h>
32     #include <stdlib.h>
33    
34    
35     char *uppercase(char *l)
36     {
37     static char staticbuf[1000];
38     int i = 0;
39    
40     while (*l && i < sizeof(staticbuf)) {
41     char u = *l++;
42     if (u >= 'a' && u <= 'z')
43     u -= 32;
44     staticbuf[i++] = u;
45     }
46     if (i == sizeof(staticbuf))
47     i--;
48     staticbuf[i] = 0;
49     return staticbuf;
50     }
51    
52    
53     int main(int argc, char *argv[])
54     {
55     char *a, *b;
56    
57     if (argc != 3) {
58     fprintf(stderr, "usage: %s arch Arch\n", argv[0]);
59     fprintf(stderr, "Example: %s alpha Alpha\n", argv[0]);
60     fprintf(stderr, " or: %s arm ARM\n", argv[0]);
61     exit(1);
62     }
63    
64     a = argv[1];
65     b = argv[2];
66    
67     printf("\n/*\n * AUTOMATICALLY GENERATED! Do not edit.\n */\n\n");
68    
69     printf("#ifdef DYNTRANS_32\n");
70     printf("#define MODE32\n");
71     printf("#endif\n");
72    
73     printf("#define DYNTRANS_FUNCTION_TRACE "
74     "%s_cpu_functioncall_trace\n", a);
75     printf("#include \"cpu_dyntrans.c\"\n");
76     printf("#undef DYNTRANS_FUNCTION_TRACE\n\n");
77    
78     printf("#define DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE "
79     "%s_tc_allocate_default_page\n", a);
80     printf("#include \"cpu_dyntrans.c\"\n");
81     printf("#undef DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE\n\n");
82    
83     printf("#define DYNTRANS_INVAL_ENTRY\n");
84     printf("#include \"cpu_dyntrans.c\"\n");
85     printf("#undef DYNTRANS_INVAL_ENTRY\n\n");
86    
87     printf("#define DYNTRANS_INVALIDATE_TC_PADDR "
88     "%s_invalidate_translation_caches_paddr\n", a);
89     printf("#include \"cpu_dyntrans.c\"\n");
90     printf("#undef DYNTRANS_INVALIDATE_TC_PADDR\n\n");
91    
92     printf("#define DYNTRANS_INVALIDATE_TC_CODE "
93     "%s_invalidate_code_translation\n", a);
94     printf("#include \"cpu_dyntrans.c\"\n");
95     printf("#undef DYNTRANS_INVALIDATE_TC_CODE\n\n");
96    
97     printf("#define DYNTRANS_UPDATE_TRANSLATION_TABLE "
98     "%s_update_translation_table\n", a);
99     printf("#include \"cpu_dyntrans.c\"\n");
100     printf("#undef DYNTRANS_UPDATE_TRANSLATION_TABLE\n\n");
101    
102     printf("#define MEMORY_RW %s_memory_rw\n", a);
103     printf("#define MEM_%s\n", uppercase(a));
104     printf("#include \"../memory_rw.c\"\n");
105     printf("#undef MEM_%s\n", uppercase(a));
106     printf("#undef MEMORY_RW\n\n");
107    
108     printf("#define DYNTRANS_PC_TO_POINTERS_FUNC %s_pc_to_pointers\n", a);
109     printf("#define DYNTRANS_PC_TO_POINTERS_GENERIC "
110     "%s_pc_to_pointers_generic\n", a);
111     printf("#include \"cpu_dyntrans.c\"\n");
112     printf("#undef DYNTRANS_PC_TO_POINTERS_FUNC\n\n");
113     printf("#undef DYNTRANS_PC_TO_POINTERS_GENERIC\n\n");
114    
115    
116     printf("#define COMBINE_INSTRUCTIONS %s_combine_instructions\n", a);
117     printf("#ifndef DYNTRANS_32\n");
118     printf("#define reg(x) (*((uint64_t *)(x)))\n");
119     printf("#define MODE_uint_t uint64_t\n");
120     printf("#define MODE_int_t int64_t\n");
121     printf("#else\n");
122     printf("#define reg(x) (*((uint32_t *)(x)))\n");
123     printf("#define MODE_uint_t uint32_t\n");
124     printf("#define MODE_int_t int32_t\n");
125     printf("#endif\n");
126     printf("#include \"cpu_%s_instr.c\"\n\n", a);
127    
128    
129     printf("#ifdef DYNTRANS_DUALMODE_32\n");
130     printf("#undef COMBINE_INSTRUCTIONS\n");
131     printf("#define COMBINE_INSTRUCTIONS %s32_combine_instructions\n", a);
132     printf("#undef X\n#undef instr\n#undef reg\n"
133     "#define X(n) void %s32_instr_ ## n(struct cpu *cpu, \\\n"
134     "\tstruct %s_instr_call *ic)\n", a, a);
135     printf("#define instr(n) %s32_instr_ ## n\n", a);
136     printf("#ifdef HOST_LITTLE_ENDIAN\n");
137     printf("#define reg(x) ( *((uint32_t *)(x)) )\n");
138     printf("#else\n");
139     printf("#define reg(x) ( *((uint32_t *)(x)+1) )\n");
140     printf("#endif\n");
141     printf("#define MODE32\n");
142     printf("#undef MODE_uint_t\n#undef MODE_int_t\n");
143     printf("#define MODE_uint_t uint32_t\n");
144     printf("#define MODE_int_t int32_t\n");
145    
146     printf("#define DYNTRANS_INVAL_ENTRY\n");
147     printf("#undef DYNTRANS_INVALIDATE_TLB_ENTRY\n"
148     "#define DYNTRANS_INVALIDATE_TLB_ENTRY "
149     "%s32_invalidate_tlb_entry\n", a);
150     printf("#include \"cpu_dyntrans.c\"\n");
151     printf("#undef DYNTRANS_INVAL_ENTRY\n\n");
152     printf("#define DYNTRANS_INVALIDATE_TC_PADDR "
153     "%s32_invalidate_translation_caches_paddr\n", a);
154     printf("#include \"cpu_dyntrans.c\"\n");
155     printf("#undef DYNTRANS_INVALIDATE_TC_PADDR\n\n");
156     printf("#define DYNTRANS_INVALIDATE_TC_CODE "
157     "%s32_invalidate_code_translation\n", a);
158     printf("#include \"cpu_dyntrans.c\"\n");
159     printf("#undef DYNTRANS_INVALIDATE_TC_CODE\n\n");
160     printf("#define DYNTRANS_UPDATE_TRANSLATION_TABLE "
161     "%s32_update_translation_table\n", a);
162     printf("#include \"cpu_dyntrans.c\"\n");
163     printf("#undef DYNTRANS_UPDATE_TRANSLATION_TABLE\n\n");
164     printf("#define DYNTRANS_PC_TO_POINTERS_FUNC %s32_pc_to_pointers\n", a);
165     printf("#define DYNTRANS_PC_TO_POINTERS_GENERIC "
166     "%s32_pc_to_pointers_generic\n", a);
167     printf("#undef DYNTRANS_PC_TO_POINTERS\n"
168     "#define DYNTRANS_PC_TO_POINTERS %s32_pc_to_pointers\n", a);
169     printf("#include \"cpu_dyntrans.c\"\n");
170     printf("#undef DYNTRANS_PC_TO_POINTERS_FUNC\n\n");
171     printf("#undef DYNTRANS_PC_TO_POINTERS_GENERIC\n\n");
172     printf("#include \"cpu_%s_instr.c\"\n", a);
173    
174     printf("\n#undef DYNTRANS_PC_TO_POINTERS\n"
175     "#define DYNTRANS_PC_TO_POINTERS %s_pc_to_pointers\n"
176     "#define DYNTRANS_PC_TO_POINTERS32 %s32_pc_to_pointers\n\n", a, a);
177    
178     printf("#endif /* DYNTRANS_DUALMODE_32 */\n\n\n");
179    
180    
181     printf("#define DYNTRANS_CPU_RUN_INSTR %s_cpu_run_instr\n", a);
182     printf("#include \"cpu_dyntrans.c\"\n");
183     printf("#undef DYNTRANS_CPU_RUN_INSTR\n\n");
184    
185     printf("#define CPU_RUN %s_cpu_run\n", a);
186     printf("#define CPU_RINSTR %s_cpu_run_instr\n", a);
187     printf("#define CPU_RUN_%s\n", uppercase(a));
188     printf("#include \"cpu_run.c\"\n");
189     printf("#undef CPU_RINSTR\n");
190     printf("#undef CPU_RUN_%s\n", uppercase(a));
191     printf("#undef CPU_RUN\n\n");
192    
193     printf("CPU_FAMILY_INIT(%s,\"%s\")\n\n", a, b);
194    
195     return 0;
196     }
197    

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