/[gxemul]/trunk/src/cpus/generate_ppc_loadstore.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/generate_ppc_loadstore.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8625 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: generate_ppc_loadstore.c,v 1.5 2006/12/30 13:30:56 debug Exp $
29 */
30
31 #include <stdio.h>
32 #include <string.h>
33
34
35 char *sizechar[4] = { "b", "h", "w", "d" };
36 char *modes[2] = { "", "32" };
37
38
39 void do_it(int mode)
40 {
41 int n, load, size, zero, ignoreofs, update;
42
43 n = 0;
44 for (update=0; update<=1; update++)
45 for (ignoreofs=0; ignoreofs<=1; ignoreofs++)
46 for (load=0; load<=1; load++)
47 for (zero=0; zero<=1; zero++)
48 for (size=0; size<4; size++) {
49 if (!zero && !load)
50 continue;
51 if (load && !zero && size == 3)
52 continue;
53
54 switch (size) {
55 case 0: printf("#define LS_B\n"); break;
56 case 1: printf("#define LS_H\n"); break;
57 case 2: printf("#define LS_W\n"); break;
58 case 3: printf("#define LS_D\n"); break;
59 }
60 printf("#define LS_SIZE %i\n", 1 << size);
61 if (zero)
62 printf("#define LS_ZERO\n");
63 if (load)
64 printf("#define LS_LOAD\n");
65 if (ignoreofs)
66 printf("#define LS_IGNOREOFS\n");
67 if (update)
68 printf("#define LS_UPDATE\n");
69
70 printf("#define LS_GENERIC_N ppc%s_generic_",
71 modes[mode]);
72 if (load)
73 printf("l");
74 else
75 printf("st");
76 printf("%s", sizechar[size]);
77 if (load) {
78 if (zero)
79 printf("z");
80 else
81 printf("a");
82 }
83 if (update)
84 printf("u");
85 printf("\n");
86
87 printf("#define LS_N ppc%s_instr_", modes[mode]);
88 if (load)
89 printf("l");
90 else
91 printf("st");
92 printf("%s", sizechar[size]);
93 if (load && size < 3) {
94 if (zero)
95 printf("z");
96 else
97 printf("a");
98 }
99 if (update)
100 printf("u");
101 if (ignoreofs)
102 printf("_0");
103 printf("\n");
104
105 printf("#include \"cpu_ppc_instr_loadstore.c\"\n");
106
107 printf("#undef LS_N\n");
108 printf("#undef LS_GENERIC_N\n");
109 switch (size) {
110 case 0: printf("#undef LS_B\n"); break;
111 case 1: printf("#undef LS_H\n"); break;
112 case 2: printf("#undef LS_W\n"); break;
113 case 3: printf("#undef LS_D\n"); break;
114 }
115 printf("#undef LS_SIZE\n");
116 if (load)
117 printf("#undef LS_LOAD\n");
118 if (update)
119 printf("#undef LS_UPDATE\n");
120 if (zero)
121 printf("#undef LS_ZERO\n");
122 if (ignoreofs)
123 printf("#undef LS_IGNOREOFS\n");
124 }
125
126 /* Indexed loads/stores: */
127 printf("#define LS_INDEXED\n");
128 for (update=0; update<=1; update++)
129 for (load=0; load<=1; load++)
130 for (zero=0; zero<=1; zero++)
131 for (size=0; size<4; size++) {
132 if (!zero && !load)
133 continue;
134 if (load && !zero && size == 3)
135 continue;
136
137 switch (size) {
138 case 0: printf("#define LS_B\n"); break;
139 case 1: printf("#define LS_H\n"); break;
140 case 2: printf("#define LS_W\n"); break;
141 case 3: printf("#define LS_D\n"); break;
142 }
143 printf("#define LS_SIZE %i\n", 1 << size);
144 if (zero)
145 printf("#define LS_ZERO\n");
146 if (load)
147 printf("#define LS_LOAD\n");
148 if (update)
149 printf("#define LS_UPDATE\n");
150
151 printf("#define LS_GENERIC_N ppc%s_generic_",
152 modes[mode]);
153 if (load)
154 printf("l");
155 else
156 printf("st");
157 printf("%s", sizechar[size]);
158 if (load) {
159 if (zero)
160 printf("z");
161 else
162 printf("a");
163 }
164 if (update)
165 printf("u");
166 printf("x");
167 printf("\n");
168
169 printf("#define LS_N ppc%s_instr_", modes[mode]);
170 if (load)
171 printf("l");
172 else
173 printf("st");
174 printf("%s", sizechar[size]);
175 if (load && size < 3) {
176 if (zero)
177 printf("z");
178 else
179 printf("a");
180 }
181 if (update)
182 printf("u");
183 printf("x");
184 printf("\n");
185
186 printf("#include \"cpu_ppc_instr_loadstore.c\"\n");
187
188 printf("#undef LS_N\n");
189 printf("#undef LS_GENERIC_N\n");
190 switch (size) {
191 case 0: printf("#undef LS_B\n"); break;
192 case 1: printf("#undef LS_H\n"); break;
193 case 2: printf("#undef LS_W\n"); break;
194 case 3: printf("#undef LS_D\n"); break;
195 }
196 printf("#undef LS_SIZE\n");
197 if (load)
198 printf("#undef LS_LOAD\n");
199 if (update)
200 printf("#undef LS_UPDATE\n");
201 if (zero)
202 printf("#undef LS_ZERO\n");
203 }
204
205 printf("#undef LS_INDEXED\n");
206
207
208 /* Lookup tables for loads/stores: */
209 printf("\n\nvoid (*ppc%s_loadstore[64])(struct cpu *, struct "
210 "ppc_instr_call *) = {\n", modes[mode]);
211 n = 0;
212 for (update=0; update<=1; update++)
213 for (ignoreofs=0; ignoreofs<=1; ignoreofs++)
214 for (load=0; load<=1; load++)
215 for (zero=0; zero<=1; zero++)
216 for (size=0; size<4; size++) {
217 printf("\tppc%s_instr_", modes[mode]);
218
219 if (load && !zero && size == 3) {
220 printf("invalid");
221 goto cont;
222 }
223
224 if (load)
225 printf("l");
226 else
227 printf("st");
228 printf("%s", sizechar[size]);
229 if (load && size < 3) {
230 if (zero)
231 printf("z");
232 else
233 printf("a");
234 }
235 if (update)
236 printf("u");
237 if (ignoreofs)
238 printf("_0");
239 cont:
240 if (++n < 64)
241 printf(",");
242 printf("\n");
243 }
244
245 printf("};\n\n");
246
247 printf("\n\nvoid (*ppc%s_loadstore_indexed[32])(struct cpu *, struct "
248 "ppc_instr_call *) = {\n", modes[mode]);
249 n = 0;
250 for (update=0; update<=1; update++)
251 for (load=0; load<=1; load++)
252 for (zero=0; zero<=1; zero++)
253 for (size=0; size<4; size++) {
254 printf("\tppc%s_instr_", modes[mode]);
255
256 if (load && !zero && size == 3) {
257 printf("invalid");
258 goto cont_x;
259 }
260
261 if (load)
262 printf("l");
263 else
264 printf("st");
265 printf("%s", sizechar[size]);
266 if (load && size < 3) {
267 if (zero)
268 printf("z");
269 else
270 printf("a");
271 }
272 if (update)
273 printf("u");
274 printf("x");
275 cont_x:
276 if (++n < 32)
277 printf(",");
278 printf("\n");
279 }
280
281 printf("};\n\n");
282
283 /* Non-standard loads/stores: */
284 printf("#define LS_BYTEREVERSE\n"
285 "#define LS_INDEXED\n"
286
287 "#define LS_SIZE 2\n"
288 "#define LS_H\n"
289 "#define LS_GENERIC_N ppc%s_generic_lhbrx\n"
290 "#define LS_N ppc%s_instr_lhbrx\n"
291 "#define LS_LOAD\n"
292 "#include \"cpu_ppc_instr_loadstore.c\"\n"
293 "#undef LS_LOAD\n"
294 "#undef LS_N\n"
295 "#undef LS_GENERIC_N\n"
296 "#define LS_GENERIC_N ppc%s_generic_sthbrx\n"
297 "#define LS_N ppc%s_instr_sthbrx\n"
298 "#include \"cpu_ppc_instr_loadstore.c\"\n"
299 "#undef LS_N\n"
300 "#undef LS_GENERIC_N\n"
301 "#undef LS_H\n"
302 "#undef LS_SIZE\n"
303
304 "#define LS_SIZE 4\n"
305 "#define LS_W\n"
306 "#define LS_GENERIC_N ppc%s_generic_lwbrx\n"
307 "#define LS_N ppc%s_instr_lwbrx\n"
308 "#define LS_LOAD\n"
309 "#include \"cpu_ppc_instr_loadstore.c\"\n"
310 "#undef LS_LOAD\n"
311 "#undef LS_N\n"
312 "#undef LS_GENERIC_N\n"
313 "#define LS_GENERIC_N ppc%s_generic_stwbrx\n"
314 "#define LS_N ppc%s_instr_stwbrx\n"
315 "#include \"cpu_ppc_instr_loadstore.c\"\n"
316 "#undef LS_N\n"
317 "#undef LS_GENERIC_N\n"
318 "#undef LS_W\n"
319 "#undef LS_SIZE\n"
320
321 "#undef LS_INDEXED\n"
322 "#undef LS_BYTEREVERSE\n",
323 modes[mode], modes[mode], modes[mode], modes[mode],
324 modes[mode], modes[mode], modes[mode], modes[mode]);
325 }
326
327 int main(int argc, char *argv[])
328 {
329 int mode;
330
331 printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
332
333 for (mode = 0; mode <= 1; mode ++) {
334 if (mode == 0)
335 printf("#ifndef MODE32\n");
336 else
337 printf("#ifdef MODE32\n");
338
339 do_it(mode);
340
341 printf("#endif\n");
342 }
343
344 return 0;
345 }
346
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