src/cpus/generate_arm_multi.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: generate_arm_multi.c,v 1.15 2006/12/30 13:30:56 debug Exp $
 *
 *  Generation of commonly used ARM load/store multiple instructions.
 *
 *  The main idea is to first check whether a load/store would be possible
 *  without going outside a page, and if so, use the host_load or _store
 *  arrays for quick access to emulated RAM. Otherwise, fall back to using
 *  the generic bdt_load() or bdt_store().
 */

#include <stdio.h>
#include <stdlib.h>

#include "misc.h"


/*
 *  generate_opcode():
 *
 *  Given an ARM load/store multiple opcode, produce equivalent "hardcoded"
 *  C code which emulates the opcode.
 *
 *  TODO:
 *
 *      o)  On 64-bit hosts, load/store two registers at a time. This
 *          feature depends both on the alignment of the base register,
 *          and the specific set of registers being loaded/stored.
 *
 *      o)  Alignment checks. (Optional?)
 *
 *      o)  For accesses that cross page boundaries, use two pages using
 *          the fast method instead of calling the generic function?
 */
void generate_opcode(uint32_t opcode)
{
        int p, u, s, w, load, r, n_regs, i, x;

        if ((opcode & 0x0e000000) != 0x08000000) {
                fprintf(stderr, "opcode 0x%08"PRIx32" is not an ldm/stm\n",
                    opcode);
                exit(1);
        }

        r = (opcode >> 16) & 15;
        p = opcode & 0x01000000? 1 : 0;
        u = opcode & 0x00800000? 1 : 0;
        s = opcode & 0x00400000? 1 : 0;
        w = opcode & 0x00200000? 1 : 0;
        load = opcode & 0x00100000? 1 : 0;
        n_regs = 0;
        for (i=0; i<16; i++)
                if (opcode & (1 << i))
                        n_regs ++;

        /*  TODO: Check for register pairs, for 64-bit load/stores  */

        if (n_regs == 0) {
                fprintf(stderr, "opcode 0x%08"PRIx32" has no registers set\n",
                    opcode);
                exit(1);
        }

        if (s) {
                fprintf(stderr, "opcode 0x%08"PRIx32" has s-bit set\n", opcode);
                exit(1);
        }

        if (r == 15) {
                fprintf(stderr, "opcode 0x%08"PRIx32" has r=15\n", opcode);
                exit(1);
        }

        printf("\nvoid arm_instr_multi_0x%08"PRIx32"(struct cpu *cpu,"
            " struct arm_instr_call *ic) {\n", opcode);

        printf("\tunsigned char *page;\n");
        printf("\tuint32_t addr = cpu->cd.arm.r[%i];\n", r);

        if (!load && opcode & 0x8000) {
                printf("\tuint32_t tmp_pc = ((size_t)ic - (size_t)\n\t"
                    "    cpu->cd.arm.cur_ic_page) / sizeof(struct "
                    "arm_instr_call);\n"
                    "\ttmp_pc = ((cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1)"
                    "\n\t    << ARM_INSTR_ALIGNMENT_SHIFT)))\n"
                    "\t    + (tmp_pc << ARM_INSTR_ALIGNMENT_SHIFT) + 12;\n");
        }

        if (p)
                printf("\taddr %s 4;\n", u? "+=" : "-=");

        printf("\tpage = cpu->cd.arm.host_%s[addr >> 12];\n",
            load? "load" : "store");

        printf("\taddr &= 0xffc;\n");

        printf("\tif (");
        switch (p*2 + u) {
        case 0: /*  post-decrement  */
                if (n_regs > 1)
                        printf("addr >= 0x%x && ", 4*(n_regs-1));
                break;
        case 1: /*  post-increment  */
                if (n_regs > 1)
                        printf("addr <= 0x%x && ", 0x1000 - 4*n_regs);
                break;
        case 2: /*  pre-decrement  */
                if (n_regs > 1)
                        printf("addr >= 0x%x && ", 4*(n_regs-1));
                break;
        case 3: /*  pre-increment  */
                if (n_regs > 1)
                        printf("addr <= 0x%x && ", 0x1000 - 4*n_regs);
                break;
        }
        printf("page != NULL) {\n");

        printf("\t\tuint32_t *p = (uint32_t *) (page + addr);\n");

        if (u) {
                x = 0;
                for (i=0; i<=15; i++) {
                        if (!(opcode & (1 << i)))
                                continue;

                        if (load && w && i == r) {
                                /*  Skip the load if we're using writeback.  */
                        } else if (load) {
                                if (i == 15)
                                        printf("\t\tcpu->pc = p[%i];\n", x);
                                else
                                        printf("\t\tcpu->cd.arm.r[%i] = "
                                            "p[%i];\n", i, x);
                        } else {
                                if (i == 15)
                                        printf("\t\tp[%i] = tmp_pc;\n", x);
                                else
                                        printf("\t\tp[%i] = cpu->cd.arm.r"
                                            "[%i];\n", x, i);
                        }

                        x ++;
                }
        } else {
                /*  Decrementing, but do it incrementing anyway:  */
                x = -n_regs;
                for (i=0; i<=15; i++) {
                        if (!(opcode & (1 << i)))
                                continue;

                        x ++;

                        if (load && w && i == r) {
                                /*  Skip the load if we're using writeback.  */
                        } else if (load) {
                                if (i == 15)
                                        printf("\t\tcpu->pc = p[%i];\n", x);
                                else
                                        printf("\t\tcpu->cd.arm.r[%i] = "
                                            "p[%i];\n", i, x);
                        } else {
                                if (i == 15)
                                        printf("\t\tp[%i] = tmp_pc;\n", x);
                                else
                                        printf("\t\tp[%i] = "
                                            "cpu->cd.arm.r[%i];\n", x, i);
                        }
                }
        }

        if (w)
                printf("\t\tcpu->cd.arm.r[%i] %s %i;\n",
                    r, u? "+=" : "-=", 4*n_regs);

        if (load && opcode & 0x8000) {
                printf("\t\tquick_pc_to_pointers(cpu);\n");
        }

        printf("\t} else\n");
        printf("\t\tinstr(bdt_%s)(cpu, ic);\n", load? "load" : "store");

        printf("}\nY(multi_0x%08"PRIx32")\n", opcode);
}


/*
 *  main():
 *
 *  Normal ARM code seems to only use about a few hundred of the 1^24 possible
 *  load/store multiple instructions. (I'm not counting the s-bit now.)
 *  Instead of having a linear array of 100s of entries, we can select a list
 *  to scan based on a few bits (*), and those lists will be shorter.
 *
 *  (*)  By running experiment_arm_multi.c on statistics gathered from running
 *       NetBSD/cats, it seems that choosing the following 8 bits results in
 *       the shortest linear lists:
 *
 *                xxxx100P USWLnnnn llllllll llllllll
 *                         ^  ^ ^ ^        ^  ^ ^ ^     (0x00950154)
 */
int main(int argc, char *argv[])
{
        int i, j;
        int n_used[256];

        if (argc < 2) {
                fprintf(stderr, "usage: %s opcode [..]\n", argv[0]);
                exit(1);
        }

        printf("\n/*  AUTOMATICALLY GENERATED! Do not edit.  */\n\n"
            "#include <stdio.h>\n"
            "#include <stdlib.h>\n"
            "#include \"cpu.h\"\n"
            "#include \"misc.h\"\n"
            "#define DYNTRANS_PC_TO_POINTERS arm_pc_to_pointers\n"
            "#include \"quick_pc_to_pointers.h\"\n"
            "#include \"arm_tmphead_1.h\"\n"
            "\n#define instr(x) arm_instr_ ## x\n");
        printf("extern void arm_pc_to_pointers(struct cpu *);\n");
        printf("extern void arm_instr_nop(struct cpu *, "
            "struct arm_instr_call *);\n");
        printf("extern void arm_instr_bdt_load(struct cpu *, "
            "struct arm_instr_call *);\n");
        printf("extern void arm_instr_bdt_store(struct cpu *, "
            "struct arm_instr_call *);\n");
        printf("\n\n");

        /*  Generate the opcode functions:  */
        for (i=1; i<argc; i++)
                generate_opcode(strtol(argv[i], NULL, 0));

        /*  Generate 256 small lookup tables:  */
        for (j=0; j<256; j++) {
                int n = 0, zz, zz0;
                for (i=1; i<argc; i++) {
                        zz = strtol(argv[i], NULL, 0);
                        zz = ((zz & 0x00800000) >> 16)
                            |((zz & 0x00100000) >> 14)
                            |((zz & 0x00040000) >> 13)
                            |((zz & 0x00010000) >> 12)
                            |((zz & 0x00000100) >>  5)
                            |((zz & 0x00000040) >>  4)
                            |((zz & 0x00000010) >>  3)
                            |((zz & 0x00000004) >>  2);
                        if (zz == j)
                                n++;
                }
                printf("\nuint32_t multi_opcode_%i[%i] = {\n", j, n+1);
                for (i=1; i<argc; i++) {
                        zz = zz0 = strtol(argv[i], NULL, 0);
                        zz = ((zz & 0x00800000) >> 16)
                            |((zz & 0x00100000) >> 14)
                            |((zz & 0x00040000) >> 13)
                            |((zz & 0x00010000) >> 12)
                            |((zz & 0x00000100) >>  5)
                            |((zz & 0x00000040) >>  4)
                            |((zz & 0x00000010) >>  3)
                            |((zz & 0x00000004) >>  2);
                        if (zz == j)
                                printf("\t0x%08x,\n", zz0);
                }
                printf("0 };\n");
        }

        /*  Generate 256 tables with function pointers:  */
        for (j=0; j<256; j++) {
                int n = 0, zz, zz0;
                for (i=1; i<argc; i++) {
                        zz = strtol(argv[i], NULL, 0);
                        zz = ((zz & 0x00800000) >> 16)
                            |((zz & 0x00100000) >> 14)
                            |((zz & 0x00040000) >> 13)
                            |((zz & 0x00010000) >> 12)
                            |((zz & 0x00000100) >>  5)
                            |((zz & 0x00000040) >>  4)
                            |((zz & 0x00000010) >>  3)
                            |((zz & 0x00000004) >>  2);
                        if (zz == j)
                                n++;
                }
                n_used[j] = n;
                if (n == 0)
                        continue;
                printf("void (*multi_opcode_f_%i[%i])(struct cpu *,"
                    " struct arm_instr_call *) = {\n", j, n*16);
                for (i=1; i<argc; i++) {
                        zz = zz0 = strtol(argv[i], NULL, 0);
                        zz = ((zz & 0x00800000) >> 16)
                            |((zz & 0x00100000) >> 14)
                            |((zz & 0x00040000) >> 13)
                            |((zz & 0x00010000) >> 12)
                            |((zz & 0x00000100) >>  5)
                            |((zz & 0x00000040) >>  4)
                            |((zz & 0x00000010) >>  3)
                            |((zz & 0x00000004) >>  2);
                        if (zz == j) {
                                printf("\tarm_instr_multi_0x%08x__eq,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__ne,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__cs,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__cc,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__mi,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__pl,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__vs,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__vc,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__hi,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__ls,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__ge,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__lt,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__gt,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x__le,\n", zz0);
                                printf("\tarm_instr_multi_0x%08x,\n", zz0);
                                printf("\tarm_instr_nop,\n");
                        }
                }
                printf("};\n");
        }


        printf("\nuint32_t *multi_opcode[256] = {\n");
        for (i=0; i<256; i++) {
                printf(" multi_opcode_%i,", i);
                if ((i % 4) == 0)
                        printf("\n");
        }
        printf("};\n");

        printf("\nvoid (**multi_opcode_f[256])(struct cpu *,"
            " struct arm_instr_call *) = {\n");
        for (i=0; i<256; i++) {
                if (n_used[i] > 0)
                        printf(" multi_opcode_f_%i,", i);
                else
                        printf(" NULL,");
                if ((i % 4) == 0)
                        printf("\n");
        }
        printf("};\n");

        return 0;
}

1	dpavlin	18	/*
2	dpavlin	34	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	dpavlin	18	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	34	* $Id: generate_arm_multi.c,v 1.15 2006/12/30 13:30:56 debug Exp $
29	dpavlin	18	*
30			* Generation of commonly used ARM load/store multiple instructions.
31	dpavlin	20	*
32	dpavlin	18	* The main idea is to first check whether a load/store would be possible
33			* without going outside a page, and if so, use the host_load or _store
34			* arrays for quick access to emulated RAM. Otherwise, fall back to using
35			* the generic bdt_load() or bdt_store().
36			*/
37
38			#include <stdio.h>
39			#include <stdlib.h>
40	dpavlin	24
41	dpavlin	18	#include "misc.h"
42
43
44			/*
45			* generate_opcode():
46			*
47			* Given an ARM load/store multiple opcode, produce equivalent "hardcoded"
48			* C code which emulates the opcode.
49			*
50			* TODO:
51			*
52			* o) On 64-bit hosts, load/store two registers at a time. This
53			* feature depends both on the alignment of the base register,
54			* and the specific set of registers being loaded/stored.
55			*
56			* o) Alignment checks. (Optional?)
57			*
58			* o) For accesses that cross page boundaries, use two pages using
59			* the fast method instead of calling the generic function?
60			*/
61			void generate_opcode(uint32_t opcode)
62			{
63			int p, u, s, w, load, r, n_regs, i, x;
64
65			if ((opcode & 0x0e000000) != 0x08000000) {
66	dpavlin	24	fprintf(stderr, "opcode 0x%08"PRIx32" is not an ldm/stm\n",
67			opcode);
68	dpavlin	18	exit(1);
69			}
70
71			r = (opcode >> 16) & 15;
72			p = opcode & 0x01000000? 1 : 0;
73			u = opcode & 0x00800000? 1 : 0;
74			s = opcode & 0x00400000? 1 : 0;
75			w = opcode & 0x00200000? 1 : 0;
76			load = opcode & 0x00100000? 1 : 0;
77			n_regs = 0;
78			for (i=0; i<16; i++)
79			if (opcode & (1 << i))
80			n_regs ++;
81
82			/* TODO: Check for register pairs, for 64-bit load/stores */
83
84			if (n_regs == 0) {
85	dpavlin	24	fprintf(stderr, "opcode 0x%08"PRIx32" has no registers set\n",
86			opcode);
87	dpavlin	18	exit(1);
88			}
89
90			if (s) {
91	dpavlin	24	fprintf(stderr, "opcode 0x%08"PRIx32" has s-bit set\n", opcode);
92	dpavlin	18	exit(1);
93			}
94
95			if (r == 15) {
96	dpavlin	24	fprintf(stderr, "opcode 0x%08"PRIx32" has r=15\n", opcode);
97	dpavlin	18	exit(1);
98			}
99
100	dpavlin	24	printf("\nvoid arm_instr_multi_0x%08"PRIx32"(struct cpu *cpu,"
101	dpavlin	20	" struct arm_instr_call *ic) {\n", opcode);
102	dpavlin	18
103			printf("\tunsigned char *page;\n");
104			printf("\tuint32_t addr = cpu->cd.arm.r[%i];\n", r);
105
106			if (!load && opcode & 0x8000) {
107			printf("\tuint32_t tmp_pc = ((size_t)ic - (size_t)\n\t"
108			" cpu->cd.arm.cur_ic_page) / sizeof(struct "
109			"arm_instr_call);\n"
110	dpavlin	20	"\ttmp_pc = ((cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1)"
111	dpavlin	18	"\n\t << ARM_INSTR_ALIGNMENT_SHIFT)))\n"
112			"\t + (tmp_pc << ARM_INSTR_ALIGNMENT_SHIFT) + 12;\n");
113			}
114
115			if (p)
116			printf("\taddr %s 4;\n", u? "+=" : "-=");
117
118			printf("\tpage = cpu->cd.arm.host_%s[addr >> 12];\n",
119			load? "load" : "store");
120
121			printf("\taddr &= 0xffc;\n");
122
123			printf("\tif (");
124			switch (p*2 + u) {
125			case 0: /* post-decrement */
126			if (n_regs > 1)
127			printf("addr >= 0x%x && ", 4*(n_regs-1));
128			break;
129			case 1: /* post-increment */
130			if (n_regs > 1)
131			printf("addr <= 0x%x && ", 0x1000 - 4*n_regs);
132			break;
133			case 2: /* pre-decrement */
134			if (n_regs > 1)
135			printf("addr >= 0x%x && ", 4*(n_regs-1));
136			break;
137			case 3: /* pre-increment */
138			if (n_regs > 1)
139			printf("addr <= 0x%x && ", 0x1000 - 4*n_regs);
140			break;
141			}
142			printf("page != NULL) {\n");
143
144			printf("\t\tuint32_t p = (uint32_t ) (page + addr);\n");
145
146			if (u) {
147			x = 0;
148			for (i=0; i<=15; i++) {
149			if (!(opcode & (1 << i)))
150			continue;
151
152			if (load && w && i == r) {
153			/* Skip the load if we're using writeback. */
154	dpavlin	20	} else if (load) {
155	dpavlin	18	if (i == 15)
156	dpavlin	20	printf("\t\tcpu->pc = p[%i];\n", x);
157			else
158			printf("\t\tcpu->cd.arm.r[%i] = "
159			"p[%i];\n", i, x);
160			} else {
161			if (i == 15)
162	dpavlin	18	printf("\t\tp[%i] = tmp_pc;\n", x);
163			else
164	dpavlin	20	printf("\t\tp[%i] = cpu->cd.arm.r"
165			"[%i];\n", x, i);
166	dpavlin	18	}
167
168			x ++;
169			}
170			} else {
171			/* Decrementing, but do it incrementing anyway: */
172			x = -n_regs;
173			for (i=0; i<=15; i++) {
174			if (!(opcode & (1 << i)))
175			continue;
176
177			x ++;
178
179			if (load && w && i == r) {
180			/* Skip the load if we're using writeback. */
181	dpavlin	20	} else if (load) {
182	dpavlin	18	if (i == 15)
183	dpavlin	20	printf("\t\tcpu->pc = p[%i];\n", x);
184			else
185			printf("\t\tcpu->cd.arm.r[%i] = "
186			"p[%i];\n", i, x);
187			} else {
188			if (i == 15)
189	dpavlin	18	printf("\t\tp[%i] = tmp_pc;\n", x);
190			else
191	dpavlin	20	printf("\t\tp[%i] = "
192			"cpu->cd.arm.r[%i];\n", x, i);
193	dpavlin	18	}
194			}
195			}
196
197			if (w)
198			printf("\t\tcpu->cd.arm.r[%i] %s %i;\n",
199			r, u? "+=" : "-=", 4*n_regs);
200
201			if (load && opcode & 0x8000) {
202	dpavlin	20	printf("\t\tquick_pc_to_pointers(cpu);\n");
203	dpavlin	18	}
204
205			printf("\t} else\n");
206			printf("\t\tinstr(bdt_%s)(cpu, ic);\n", load? "load" : "store");
207
208	dpavlin	24	printf("}\nY(multi_0x%08"PRIx32")\n", opcode);
209	dpavlin	18	}
210
211
212			/*
213			* main():
214			*
215			* Normal ARM code seems to only use about a few hundred of the 1^24 possible
216			* load/store multiple instructions. (I'm not counting the s-bit now.)
217			* Instead of having a linear array of 100s of entries, we can select a list
218			* to scan based on a few bits (*), and those lists will be shorter.
219			*
220			* (*) By running experiment_arm_multi.c on statistics gathered from running
221			* NetBSD/cats, it seems that choosing the following 8 bits results in
222			* the shortest linear lists:
223			*
224			* xxxx100P USWLnnnn llllllll llllllll
225			* ^ ^ ^ ^ ^ ^ ^ ^ (0x00950154)
226			*/
227			int main(int argc, char *argv[])
228			{
229			int i, j;
230			int n_used[256];
231
232			if (argc < 2) {
233			fprintf(stderr, "usage: %s opcode [..]\n", argv[0]);
234			exit(1);
235			}
236
237	dpavlin	20	printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n"
238			"#include <stdio.h>\n"
239			"#include <stdlib.h>\n"
240			"#include \"cpu.h\"\n"
241			"#include \"misc.h\"\n"
242	dpavlin	22	"#define DYNTRANS_PC_TO_POINTERS arm_pc_to_pointers\n"
243			"#include \"quick_pc_to_pointers.h\"\n"
244	dpavlin	20	"#include \"arm_tmphead_1.h\"\n"
245			"\n#define instr(x) arm_instr_ ## x\n");
246	dpavlin	22	printf("extern void arm_pc_to_pointers(struct cpu *);\n");
247	dpavlin	20	printf("extern void arm_instr_nop(struct cpu *, "
248			"struct arm_instr_call *);\n");
249			printf("extern void arm_instr_bdt_load(struct cpu *, "
250			"struct arm_instr_call *);\n");
251			printf("extern void arm_instr_bdt_store(struct cpu *, "
252			"struct arm_instr_call *);\n");
253			printf("\n\n");
254	dpavlin	18
255			/* Generate the opcode functions: */
256			for (i=1; i<argc; i++)
257			generate_opcode(strtol(argv[i], NULL, 0));
258
259			/* Generate 256 small lookup tables: */
260			for (j=0; j<256; j++) {
261			int n = 0, zz, zz0;
262			for (i=1; i<argc; i++) {
263			zz = strtol(argv[i], NULL, 0);
264			zz = ((zz & 0x00800000) >> 16)
265			\|((zz & 0x00100000) >> 14)
266			\|((zz & 0x00040000) >> 13)
267			\|((zz & 0x00010000) >> 12)
268			\|((zz & 0x00000100) >> 5)
269			\|((zz & 0x00000040) >> 4)
270			\|((zz & 0x00000010) >> 3)
271			\|((zz & 0x00000004) >> 2);
272			if (zz == j)
273			n++;
274			}
275			printf("\nuint32_t multi_opcode_%i[%i] = {\n", j, n+1);
276			for (i=1; i<argc; i++) {
277			zz = zz0 = strtol(argv[i], NULL, 0);
278			zz = ((zz & 0x00800000) >> 16)
279			\|((zz & 0x00100000) >> 14)
280			\|((zz & 0x00040000) >> 13)
281			\|((zz & 0x00010000) >> 12)
282			\|((zz & 0x00000100) >> 5)
283			\|((zz & 0x00000040) >> 4)
284			\|((zz & 0x00000010) >> 3)
285			\|((zz & 0x00000004) >> 2);
286			if (zz == j)
287			printf("\t0x%08x,\n", zz0);
288			}
289			printf("0 };\n");
290			}
291
292			/* Generate 256 tables with function pointers: */
293			for (j=0; j<256; j++) {
294			int n = 0, zz, zz0;
295			for (i=1; i<argc; i++) {
296			zz = strtol(argv[i], NULL, 0);
297			zz = ((zz & 0x00800000) >> 16)
298			\|((zz & 0x00100000) >> 14)
299			\|((zz & 0x00040000) >> 13)
300			\|((zz & 0x00010000) >> 12)
301			\|((zz & 0x00000100) >> 5)
302			\|((zz & 0x00000040) >> 4)
303			\|((zz & 0x00000010) >> 3)
304			\|((zz & 0x00000004) >> 2);
305			if (zz == j)
306			n++;
307			}
308			n_used[j] = n;
309			if (n == 0)
310			continue;
311			printf("void (multi_opcode_f_%i[%i])(struct cpu ,"
312			" struct arm_instr_call ) = {\n", j, n16);
313			for (i=1; i<argc; i++) {
314			zz = zz0 = strtol(argv[i], NULL, 0);
315			zz = ((zz & 0x00800000) >> 16)
316			\|((zz & 0x00100000) >> 14)
317			\|((zz & 0x00040000) >> 13)
318			\|((zz & 0x00010000) >> 12)
319			\|((zz & 0x00000100) >> 5)
320			\|((zz & 0x00000040) >> 4)
321			\|((zz & 0x00000010) >> 3)
322			\|((zz & 0x00000004) >> 2);
323			if (zz == j) {
324			printf("\tarm_instr_multi_0x%08x__eq,\n", zz0);
325			printf("\tarm_instr_multi_0x%08x__ne,\n", zz0);
326			printf("\tarm_instr_multi_0x%08x__cs,\n", zz0);
327			printf("\tarm_instr_multi_0x%08x__cc,\n", zz0);
328			printf("\tarm_instr_multi_0x%08x__mi,\n", zz0);
329			printf("\tarm_instr_multi_0x%08x__pl,\n", zz0);
330			printf("\tarm_instr_multi_0x%08x__vs,\n", zz0);
331			printf("\tarm_instr_multi_0x%08x__vc,\n", zz0);
332			printf("\tarm_instr_multi_0x%08x__hi,\n", zz0);
333			printf("\tarm_instr_multi_0x%08x__ls,\n", zz0);
334			printf("\tarm_instr_multi_0x%08x__ge,\n", zz0);
335			printf("\tarm_instr_multi_0x%08x__lt,\n", zz0);
336			printf("\tarm_instr_multi_0x%08x__gt,\n", zz0);
337			printf("\tarm_instr_multi_0x%08x__le,\n", zz0);
338			printf("\tarm_instr_multi_0x%08x,\n", zz0);
339			printf("\tarm_instr_nop,\n");
340			}
341			}
342			printf("};\n");
343			}
344
345
346			printf("\nuint32_t *multi_opcode[256] = {\n");
347			for (i=0; i<256; i++) {
348			printf(" multi_opcode_%i,", i);
349			if ((i % 4) == 0)
350			printf("\n");
351			}
352			printf("};\n");
353
354			printf("\nvoid (*multi_opcode_f[256])(struct cpu ,"
355			" struct arm_instr_call *) = {\n");
356			for (i=0; i<256; i++) {
357			if (n_used[i] > 0)
358			printf(" multi_opcode_f_%i,", i);
359			else
360			printf(" NULL,");
361			if ((i % 4) == 0)
362			printf("\n");
363			}
364			printf("};\n");
365
366			return 0;
367			}
368