/[gxemul]/trunk/src/cpus/generate_arm_multi.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Diff of /trunk/src/cpus/generate_arm_multi.c

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: generate_arm_multi.c,v 1.12 2005/11/30 16:23:08 debug Exp $   *  $Id: generate_arm_multi.c,v 1.14 2006/06/20 04:02:45 debug Exp $
29   *   *
30   *  Generation of commonly used ARM load/store multiple instructions.   *  Generation of commonly used ARM load/store multiple instructions.
31   *   *
# Line 37  Line 37 
37    
38  #include <stdio.h>  #include <stdio.h>
39  #include <stdlib.h>  #include <stdlib.h>
40    
41  #include "misc.h"  #include "misc.h"
42    
43    
# Line 62  void generate_opcode(uint32_t opcode) Line 63  void generate_opcode(uint32_t opcode)
63          int p, u, s, w, load, r, n_regs, i, x;          int p, u, s, w, load, r, n_regs, i, x;
64    
65          if ((opcode & 0x0e000000) != 0x08000000) {          if ((opcode & 0x0e000000) != 0x08000000) {
66                  fprintf(stderr, "opcode 0x%08x is not an ldm/stm\n", opcode);                  fprintf(stderr, "opcode 0x%08"PRIx32" is not an ldm/stm\n",
67                        opcode);
68                  exit(1);                  exit(1);
69          }          }
70    
# Line 80  void generate_opcode(uint32_t opcode) Line 82  void generate_opcode(uint32_t opcode)
82          /*  TODO: Check for register pairs, for 64-bit load/stores  */          /*  TODO: Check for register pairs, for 64-bit load/stores  */
83    
84          if (n_regs == 0) {          if (n_regs == 0) {
85                  fprintf(stderr, "opcode 0x%08x has no registers set\n", opcode);                  fprintf(stderr, "opcode 0x%08"PRIx32" has no registers set\n",
86                        opcode);
87                  exit(1);                  exit(1);
88          }          }
89    
90          if (s) {          if (s) {
91                  fprintf(stderr, "opcode 0x%08x has s-bit set\n", opcode);                  fprintf(stderr, "opcode 0x%08"PRIx32" has s-bit set\n", opcode);
92                  exit(1);                  exit(1);
93          }          }
94    
95          if (r == 15) {          if (r == 15) {
96                  fprintf(stderr, "opcode 0x%08x has r=15\n", opcode);                  fprintf(stderr, "opcode 0x%08"PRIx32" has r=15\n", opcode);
97                  exit(1);                  exit(1);
98          }          }
99    
100          printf("\nvoid arm_instr_multi_0x%08x(struct cpu *cpu,"          printf("\nvoid arm_instr_multi_0x%08"PRIx32"(struct cpu *cpu,"
101              " struct arm_instr_call *ic) {\n", opcode);              " struct arm_instr_call *ic) {\n", opcode);
102    
103          printf("\tunsigned char *page;\n");          printf("\tunsigned char *page;\n");
# Line 202  void generate_opcode(uint32_t opcode) Line 205  void generate_opcode(uint32_t opcode)
205          printf("\t} else\n");          printf("\t} else\n");
206          printf("\t\tinstr(bdt_%s)(cpu, ic);\n", load? "load" : "store");          printf("\t\tinstr(bdt_%s)(cpu, ic);\n", load? "load" : "store");
207    
208          printf("}\nY(multi_0x%08x)\n", opcode);          printf("}\nY(multi_0x%08"PRIx32")\n", opcode);
209  }  }
210    
211    
Legend:
Removed from v.22  
changed lines
  Added in v.24
  ViewVC Help
Powered by ViewVC 1.1.26