/[gxemul]/trunk/src/cpus/generate_arm_loadstore.c
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Contents of /trunk/src/cpus/generate_arm_loadstore.c

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Revision 14 - (show annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 10156 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: generate_arm_loadstore.c,v 1.1 2005/08/29 14:36:41 debug Exp $
29 */
30
31 #include <stdio.h>
32
33 char *cond[16] = {
34 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
35 "hi", "ls", "ge", "lt", "gt", "le", "", "" };
36
37 int main(int argc, char *argv[])
38 {
39 int l, b, w, h, s, u, p, reg, c, n;
40
41 printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
42 printf("#include <stdio.h>\n#include <stdlib.h>\n"
43 "#include \"cpu.h\"\n"
44 "#include \"memory.h\"\n"
45 "#include \"misc.h\"\n"
46 "#define reg(x) (*((uint32_t *)(x)))\n");
47 printf("extern void arm_instr_nop(struct cpu *, "
48 "struct arm_instr_call *);\n");
49 printf("extern void arm_instr_invalid(struct cpu *, "
50 "struct arm_instr_call *);\n");
51 printf("extern uint32_t R(struct cpu *, struct arm_instr_call *,"
52 " uint32_t, int);\n");
53 printf("extern void arm_pc_to_pointers(struct cpu *);\n");
54
55 for (reg=0; reg<=1; reg++)
56 for (p=0; p<=1; p++)
57 for (u=0; u<=1; u++)
58 for (b=0; b<=1; b++)
59 for (w=0; w<=1; w++)
60 for (l=0; l<=1; l++) {
61 printf("#define A__NAME__general arm_instr_%s_"
62 "%s_%s_%s_%s_%s__general\n",
63 l?"load":"store", w? "w1" : "w0",
64 b? "byte" : "word", u? "u1" : "u0",
65 p? "p1" : "p0", reg? "reg" : "imm");
66
67 printf("#define A__NAME arm_instr_%s_%s_%s_%s_%s_%s\n",
68 l? "load" : "store", w? "w1" : "w0",
69 b? "byte" : "word", u? "u1" : "u0",
70 p? "p1" : "p0", reg? "reg" : "imm");
71 for (c=0; c<14; c++)
72 printf("#define A__NAME__%s arm_instr_%s_"
73 "%s_%s_%s_%s_%s__%s\n",
74 cond[c], l?"load":"store", w? "w1" : "w0",
75 b? "byte" : "word", u? "u1" : "u0",
76 p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
77
78 printf("#define A__NAME_PC arm_instr_%s_%s_%s_%s_"
79 "%s_%s_pc\n", l? "load" : "store", w? "w1" : "w0",
80 b? "byte" : "word", u? "u1" : "u0",
81 p? "p1" : "p0", reg? "reg" : "imm");
82 for (c=0; c<14; c++)
83 printf("#define A__NAME_PC__%s arm_instr_%s_"
84 "%s_%s_%s_%s_%s_pc__%s\n",
85 cond[c], l?"load":"store", w? "w1" : "w0",
86 b? "byte" : "word", u? "u1" : "u0",
87 p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
88
89 if (l) printf("#define A__L\n");
90 if (w) printf("#define A__W\n");
91 if (b) printf("#define A__B\n");
92 if (u) printf("#define A__U\n");
93 if (p) printf("#define A__P\n");
94 if (reg)printf("#define A__REG\n");
95 printf("#include \"cpu_arm_instr_loadstore.c\"\n");
96 if (l) printf("#undef A__L\n");
97 if (w) printf("#undef A__W\n");
98 if (b) printf("#undef A__B\n");
99 if (u) printf("#undef A__U\n");
100 if (p) printf("#undef A__P\n");
101 if (reg)printf("#undef A__REG\n");
102 for (c=0; c<14; c++)
103 printf("#undef A__NAME__%s\n", cond[c]);
104 for (c=0; c<14; c++)
105 printf("#undef A__NAME_PC__%s\n", cond[c]);
106 printf("#undef A__NAME__general\n");
107 printf("#undef A__NAME_PC\n");
108 printf("#undef A__NAME\n");
109 }
110
111 printf("\n\tvoid (*arm_load_store_instr[1024])(struct cpu *,\n"
112 "\t\tstruct arm_instr_call *) = {\n");
113 n = 0;
114 for (reg=0; reg<=1; reg++)
115 for (p=0; p<=1; p++)
116 for (u=0; u<=1; u++)
117 for (b=0; b<=1; b++)
118 for (w=0; w<=1; w++)
119 for (l=0; l<=1; l++)
120 for (c=0; c<16; c++) {
121 if (c == 15)
122 printf("\tarm_instr_nop");
123 else
124 printf("\tarm_instr_%s_%s_%s_%s_%s_%s%s%s",
125 l? "load" : "store",
126 w? "w1" : "w0",
127 b? "byte" : "word",
128 u? "u1" : "u0",
129 p? "p1" : "p0",
130 reg? "reg" : "imm",
131 c!=14? "__" : "", cond[c]);
132 n++;
133 if (n!=2*2*2*2*2*2*16)
134 printf(",");
135 printf("\n");
136 }
137
138 printf("};\n\n");
139
140 /* Load/store with the pc register: */
141 printf("\n\tvoid (*arm_load_store_instr_pc[1024])(struct cpu *,\n"
142 "\t\tstruct arm_instr_call *) = {\n");
143 n = 0;
144 for (reg=0; reg<=1; reg++)
145 for (p=0; p<=1; p++)
146 for (u=0; u<=1; u++)
147 for (b=0; b<=1; b++)
148 for (w=0; w<=1; w++)
149 for (l=0; l<=1; l++)
150 for (c=0; c<16; c++) {
151 if (c == 15)
152 printf("\tarm_instr_nop");
153 else
154 printf("\tarm_instr_%s_%s_%s_%s_%s_%s_pc%s%s",
155 l? "load" : "store",
156 w? "w1" : "w0",
157 b? "byte" : "word",
158 u? "u1" : "u0",
159 p? "p1" : "p0",
160 reg? "reg" : "imm",
161 c!=14? "__" : "", cond[c]);
162 n++;
163 if (n!=2*2*2*2*2*2*16)
164 printf(",");
165 printf("\n");
166 }
167
168 printf("};\n\n");
169
170
171
172 /* "Addressing mode 3": */
173
174 for (reg=0; reg<=1; reg++)
175 for (p=0; p<=1; p++)
176 for (u=0; u<=1; u++)
177 for (h=0; h<=1; h++)
178 for (w=0; w<=1; w++)
179 for (s=0; s<=1; s++)
180 for (l=0; l<=1; l++) {
181 if (s==0 && h==0)
182 continue;
183 if (s==1 && l==0)
184 continue;
185
186 printf("#define A__NAME__general arm_instr_%s_"
187 "%s_%s_%s_%s_%s_%s__general\n",
188 l?"load":"store", w? "w1" : "w0",
189 s? "signed" : "unsigned",
190 h? "halfword" : "byte", u? "u1" : "u0",
191 p? "p1" : "p0", reg? "reg" : "imm");
192
193 printf("#define A__NAME arm_instr_%s_%s_%s_%s_"
194 "%s_%s_%s\n", l? "load" : "store", w? "w1" : "w0",
195 s? "signed" : "unsigned",
196 h? "halfword" : "byte", u? "u1" : "u0",
197 p? "p1" : "p0", reg? "reg" : "imm");
198 for (c=0; c<14; c++)
199 printf("#define A__NAME__%s arm_instr_%s_"
200 "%s_%s_%s_%s_%s_%s__%s\n",
201 cond[c], l?"load":"store", w? "w1" : "w0",
202 s? "signed" : "unsigned",
203 h? "halfword" : "byte", u? "u1" : "u0",
204 p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
205
206 printf("#define A__NAME_PC arm_instr_%s_%s_%s_%s_%s_"
207 "%s_%s_pc\n", l? "load" : "store", w? "w1" : "w0",
208 s? "signed" : "unsigned",
209 h? "halfword" : "byte", u? "u1" : "u0",
210 p? "p1" : "p0", reg? "reg" : "imm");
211 for (c=0; c<14; c++)
212 printf("#define A__NAME_PC__%s arm_instr_%s_"
213 "%s_%s_%s_%s_%s_%s_pc__%s\n",
214 cond[c], l?"load":"store", w? "w1" : "w0",
215 s? "signed" : "unsigned",
216 h? "halfword" : "byte", u? "u1" : "u0",
217 p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
218
219 if (s) printf("#define A__SIGNED\n");
220 if (l) printf("#define A__L\n");
221 if (w) printf("#define A__W\n");
222 if (h) printf("#define A__H\n");
223 else printf("#define A__B\n");
224 if (u) printf("#define A__U\n");
225 if (p) printf("#define A__P\n");
226 if (reg)printf("#define A__REG\n");
227 printf("#include \"cpu_arm_instr_loadstore.c\"\n");
228 if (s) printf("#undef A__SIGNED\n");
229 if (l) printf("#undef A__L\n");
230 if (w) printf("#undef A__W\n");
231 if (h) printf("#undef A__H\n");
232 else printf("#undef A__B\n");
233 if (u) printf("#undef A__U\n");
234 if (p) printf("#undef A__P\n");
235 if (reg)printf("#undef A__REG\n");
236 for (c=0; c<14; c++)
237 printf("#undef A__NAME__%s\n", cond[c]);
238 for (c=0; c<14; c++)
239 printf("#undef A__NAME_PC__%s\n", cond[c]);
240 printf("#undef A__NAME__general\n");
241 printf("#undef A__NAME_PC\n");
242 printf("#undef A__NAME\n");
243 }
244
245 printf("\n\tvoid (*arm_load_store_instr_3[2048])(struct cpu *,\n"
246 "\t\tstruct arm_instr_call *) = {\n");
247 n = 0;
248 for (reg=0; reg<=1; reg++)
249 for (p=0; p<=1; p++)
250 for (u=0; u<=1; u++)
251 for (h=0; h<=1; h++)
252 for (w=0; w<=1; w++)
253 for (s=0; s<=1; s++)
254 for (l=0; l<=1; l++)
255 for (c=0; c<16; c++) {
256 if (c == 15)
257 printf("\tarm_instr_nop");
258 else if (s==0 && h==0)
259 printf("\tarm_instr_invalid");
260 else if (s==1 && l==0)
261 printf("\tarm_instr_invalid");
262 else
263 printf("\tarm_instr_%s_%s_%s_%s_%s_%s_%s%s%s",
264 l? "load" : "store",
265 w? "w1" : "w0",
266 s? "signed" : "unsigned",
267 h? "halfword" : "byte",
268 u? "u1" : "u0", p? "p1" : "p0",
269 reg? "reg" : "imm",
270 c!=14? "__" : "", cond[c]);
271 n++;
272 if (n!=2*2*2*2*2*2*2*16)
273 printf(",");
274 printf("\n");
275 }
276
277 printf("};\n\n");
278
279 /* Load/store with the pc register: */
280 printf("\n\tvoid (*arm_load_store_instr_3_pc[2048])(struct cpu *,\n"
281 "\t\tstruct arm_instr_call *) = {\n");
282 n = 0;
283 for (reg=0; reg<=1; reg++)
284 for (p=0; p<=1; p++)
285 for (u=0; u<=1; u++)
286 for (h=0; h<=1; h++)
287 for (w=0; w<=1; w++)
288 for (s=0; s<=1; s++)
289 for (l=0; l<=1; l++)
290 for (c=0; c<16; c++) {
291 if (c == 15)
292 printf("\tarm_instr_nop");
293 else if (s==0 && h==0)
294 printf("\tarm_instr_invalid");
295 else if (s==1 && l==0)
296 printf("\tarm_instr_invalid");
297 else
298 printf("\tarm_instr_%s_%s_%s_%s_%s_%s_"
299 "%s_pc%s%s", l? "load" : "store",
300 w? "w1" : "w0",
301 s? "signed" : "unsigned",
302 h? "halfword" : "byte",
303 u? "u1" : "u0", p? "p1" : "p0",
304 reg? "reg" : "imm",
305 c!=14? "__" : "", cond[c]);
306 n++;
307 if (n!=2*2*2*2*2*2*2*16)
308 printf(",");
309 printf("\n");
310 }
311
312 printf("};\n\n");
313
314
315 return 0;
316 }
317

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