/[gxemul]/trunk/src/cpus/generate_arm_loadstore.c
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Contents of /trunk/src/cpus/generate_arm_loadstore.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 10118 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: generate_arm_loadstore.c,v 1.6 2006/02/16 19:49:04 debug Exp $
29 */
30
31 #include <stdio.h>
32
33 char *cond[16] = {
34 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
35 "hi", "ls", "ge", "lt", "gt", "le", "", "" };
36
37 int main(int argc, char *argv[])
38 {
39 int l, b, w, h, s, u, p, reg, c, n;
40
41 printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
42 printf("#include <stdio.h>\n#include <stdlib.h>\n"
43 "#include \"cpu.h\"\n"
44 "#include \"machine.h\"\n"
45 "#include \"memory.h\"\n"
46 "#include \"misc.h\"\n"
47 "#define DYNTRANS_PC_TO_POINTERS arm_pc_to_pointers\n"
48 "#include \"quick_pc_to_pointers.h\"\n"
49 "#define reg(x) (*((uint32_t *)(x)))\n");
50 printf("extern void arm_instr_nop(struct cpu *, "
51 "struct arm_instr_call *);\n");
52 printf("extern void arm_instr_invalid(struct cpu *, "
53 "struct arm_instr_call *);\n");
54 printf("extern void arm_pc_to_pointers(struct cpu *);\n");
55
56 for (reg=0; reg<=1; reg++)
57 for (p=0; p<=1; p++)
58 for (u=0; u<=1; u++)
59 for (b=0; b<=1; b++)
60 for (w=0; w<=1; w++)
61 for (l=0; l<=1; l++) {
62 printf("#define A__NAME__general arm_instr_%s_"
63 "%s_%s_%s_%s_%s__general\n",
64 l?"load":"store", w? "w1" : "w0",
65 b? "byte" : "word", u? "u1" : "u0",
66 p? "p1" : "p0", reg? "reg" : "imm");
67
68 printf("#define A__NAME arm_instr_%s_%s_%s_%s_%s_%s\n",
69 l? "load" : "store", w? "w1" : "w0",
70 b? "byte" : "word", u? "u1" : "u0",
71 p? "p1" : "p0", reg? "reg" : "imm");
72 for (c=0; c<14; c++)
73 printf("#define A__NAME__%s arm_instr_%s_"
74 "%s_%s_%s_%s_%s__%s\n",
75 cond[c], l?"load":"store", w? "w1" : "w0",
76 b? "byte" : "word", u? "u1" : "u0",
77 p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
78
79 printf("#define A__NAME_PC arm_instr_%s_%s_%s_%s_"
80 "%s_%s_pc\n", l? "load" : "store", w? "w1" : "w0",
81 b? "byte" : "word", u? "u1" : "u0",
82 p? "p1" : "p0", reg? "reg" : "imm");
83 for (c=0; c<14; c++)
84 printf("#define A__NAME_PC__%s arm_instr_%s_"
85 "%s_%s_%s_%s_%s_pc__%s\n",
86 cond[c], l?"load":"store", w? "w1" : "w0",
87 b? "byte" : "word", u? "u1" : "u0",
88 p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
89
90 if (l) printf("#define A__L\n");
91 if (w) printf("#define A__W\n");
92 if (b) printf("#define A__B\n");
93 if (u) printf("#define A__U\n");
94 if (p) printf("#define A__P\n");
95 if (reg)printf("#define A__REG\n");
96 printf("#include \"cpu_arm_instr_loadstore.c\"\n");
97 if (l) printf("#undef A__L\n");
98 if (w) printf("#undef A__W\n");
99 if (b) printf("#undef A__B\n");
100 if (u) printf("#undef A__U\n");
101 if (p) printf("#undef A__P\n");
102 if (reg)printf("#undef A__REG\n");
103 for (c=0; c<14; c++)
104 printf("#undef A__NAME__%s\n", cond[c]);
105 for (c=0; c<14; c++)
106 printf("#undef A__NAME_PC__%s\n", cond[c]);
107 printf("#undef A__NAME__general\n");
108 printf("#undef A__NAME_PC\n");
109 printf("#undef A__NAME\n");
110 }
111
112 printf("\n\tvoid (*arm_load_store_instr[1024])(struct cpu *,\n"
113 "\t\tstruct arm_instr_call *) = {\n");
114 n = 0;
115 for (reg=0; reg<=1; reg++)
116 for (p=0; p<=1; p++)
117 for (u=0; u<=1; u++)
118 for (b=0; b<=1; b++)
119 for (w=0; w<=1; w++)
120 for (l=0; l<=1; l++)
121 for (c=0; c<16; c++) {
122 if (c == 15)
123 printf("\tarm_instr_nop");
124 else
125 printf("\tarm_instr_%s_%s_%s_%s_%s_%s%s%s",
126 l? "load" : "store",
127 w? "w1" : "w0",
128 b? "byte" : "word",
129 u? "u1" : "u0",
130 p? "p1" : "p0",
131 reg? "reg" : "imm",
132 c!=14? "__" : "", cond[c]);
133 n++;
134 if (n!=2*2*2*2*2*2*16)
135 printf(",");
136 printf("\n");
137 }
138
139 printf("};\n\n");
140
141 /* Load/store with the pc register: */
142 printf("\n\tvoid (*arm_load_store_instr_pc[1024])(struct cpu *,\n"
143 "\t\tstruct arm_instr_call *) = {\n");
144 n = 0;
145 for (reg=0; reg<=1; reg++)
146 for (p=0; p<=1; p++)
147 for (u=0; u<=1; u++)
148 for (b=0; b<=1; b++)
149 for (w=0; w<=1; w++)
150 for (l=0; l<=1; l++)
151 for (c=0; c<16; c++) {
152 if (c == 15)
153 printf("\tarm_instr_nop");
154 else
155 printf("\tarm_instr_%s_%s_%s_%s_%s_%s_pc%s%s",
156 l? "load" : "store",
157 w? "w1" : "w0",
158 b? "byte" : "word",
159 u? "u1" : "u0",
160 p? "p1" : "p0",
161 reg? "reg" : "imm",
162 c!=14? "__" : "", cond[c]);
163 n++;
164 if (n!=2*2*2*2*2*2*16)
165 printf(",");
166 printf("\n");
167 }
168
169 printf("};\n\n");
170
171
172
173 /* "Addressing mode 3": */
174
175 for (reg=0; reg<=1; reg++)
176 for (p=0; p<=1; p++)
177 for (u=0; u<=1; u++)
178 for (h=0; h<=1; h++)
179 for (w=0; w<=1; w++)
180 for (s=0; s<=1; s++)
181 for (l=0; l<=1; l++) {
182 if (s==0 && h==0)
183 continue;
184 /* l=0, s=1, h=0 means LDRD */
185 /* l=0, s=1, h=1 means STRD */
186
187 printf("#define A__NAME__general arm_instr_%s_"
188 "%s_%s_%s_%s_%s_%s__general\n",
189 l?"load":"store", w? "w1" : "w0",
190 s? "signed" : "unsigned",
191 h? "halfword" : "byte", u? "u1" : "u0",
192 p? "p1" : "p0", reg? "reg" : "imm");
193
194 printf("#define A__NAME arm_instr_%s_%s_%s_%s_"
195 "%s_%s_%s\n", l? "load" : "store", w? "w1" : "w0",
196 s? "signed" : "unsigned",
197 h? "halfword" : "byte", u? "u1" : "u0",
198 p? "p1" : "p0", reg? "reg" : "imm");
199 for (c=0; c<14; c++)
200 printf("#define A__NAME__%s arm_instr_%s_"
201 "%s_%s_%s_%s_%s_%s__%s\n",
202 cond[c], l?"load":"store", w? "w1" : "w0",
203 s? "signed" : "unsigned",
204 h? "halfword" : "byte", u? "u1" : "u0",
205 p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
206
207 printf("#define A__NAME_PC arm_instr_%s_%s_%s_%s_%s_"
208 "%s_%s_pc\n", l? "load" : "store", w? "w1" : "w0",
209 s? "signed" : "unsigned",
210 h? "halfword" : "byte", u? "u1" : "u0",
211 p? "p1" : "p0", reg? "reg" : "imm");
212 for (c=0; c<14; c++)
213 printf("#define A__NAME_PC__%s arm_instr_%s_"
214 "%s_%s_%s_%s_%s_%s_pc__%s\n",
215 cond[c], l?"load":"store", w? "w1" : "w0",
216 s? "signed" : "unsigned",
217 h? "halfword" : "byte", u? "u1" : "u0",
218 p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
219
220 if (s) printf("#define A__SIGNED\n");
221 if (l) printf("#define A__L\n");
222 if (w) printf("#define A__W\n");
223 if (h) printf("#define A__H\n");
224 else printf("#define A__B\n");
225 if (u) printf("#define A__U\n");
226 if (p) printf("#define A__P\n");
227 if (reg)printf("#define A__REG\n");
228 printf("#include \"cpu_arm_instr_loadstore.c\"\n");
229 if (s) printf("#undef A__SIGNED\n");
230 if (l) printf("#undef A__L\n");
231 if (w) printf("#undef A__W\n");
232 if (h) printf("#undef A__H\n");
233 else printf("#undef A__B\n");
234 if (u) printf("#undef A__U\n");
235 if (p) printf("#undef A__P\n");
236 if (reg)printf("#undef A__REG\n");
237 for (c=0; c<14; c++)
238 printf("#undef A__NAME__%s\n", cond[c]);
239 for (c=0; c<14; c++)
240 printf("#undef A__NAME_PC__%s\n", cond[c]);
241 printf("#undef A__NAME__general\n");
242 printf("#undef A__NAME_PC\n");
243 printf("#undef A__NAME\n");
244 }
245
246 printf("\n\tvoid (*arm_load_store_instr_3[2048])(struct cpu *,\n"
247 "\t\tstruct arm_instr_call *) = {\n");
248 n = 0;
249 for (reg=0; reg<=1; reg++)
250 for (p=0; p<=1; p++)
251 for (u=0; u<=1; u++)
252 for (h=0; h<=1; h++)
253 for (w=0; w<=1; w++)
254 for (s=0; s<=1; s++)
255 for (l=0; l<=1; l++)
256 for (c=0; c<16; c++) {
257 if (c == 15)
258 printf("\tarm_instr_nop");
259 else if (s==0 && h==0)
260 printf("\tarm_instr_invalid");
261 else
262 printf("\tarm_instr_%s_%s_%s_%s_%s_%s_%s%s%s",
263 l? "load" : "store",
264 w? "w1" : "w0",
265 s? "signed" : "unsigned",
266 h? "halfword" : "byte",
267 u? "u1" : "u0", p? "p1" : "p0",
268 reg? "reg" : "imm",
269 c!=14? "__" : "", cond[c]);
270 n++;
271 if (n!=2*2*2*2*2*2*2*16)
272 printf(",");
273 printf("\n");
274 }
275
276 printf("};\n\n");
277
278 /* Load/store with the pc register: */
279 printf("\n\tvoid (*arm_load_store_instr_3_pc[2048])(struct cpu *,\n"
280 "\t\tstruct arm_instr_call *) = {\n");
281 n = 0;
282 for (reg=0; reg<=1; reg++)
283 for (p=0; p<=1; p++)
284 for (u=0; u<=1; u++)
285 for (h=0; h<=1; h++)
286 for (w=0; w<=1; w++)
287 for (s=0; s<=1; s++)
288 for (l=0; l<=1; l++)
289 for (c=0; c<16; c++) {
290 if (c == 15)
291 printf("\tarm_instr_nop");
292 else if (s==0 && h==0)
293 printf("\tarm_instr_invalid");
294 else
295 printf("\tarm_instr_%s_%s_%s_%s_%s_%s_"
296 "%s_pc%s%s", l? "load" : "store",
297 w? "w1" : "w0",
298 s? "signed" : "unsigned",
299 h? "halfword" : "byte",
300 u? "u1" : "u0", p? "p1" : "p0",
301 reg? "reg" : "imm",
302 c!=14? "__" : "", cond[c]);
303 n++;
304 if (n!=2*2*2*2*2*2*2*16)
305 printf(",");
306 printf("\n");
307 }
308
309 printf("};\n\n");
310
311
312 return 0;
313 }
314

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