/[gxemul]/trunk/src/cpus/generate_arm_loadstore.c
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Annotation of /trunk/src/cpus/generate_arm_loadstore.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 12263 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 dpavlin 14 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: generate_arm_loadstore.c,v 1.9 2007/06/04 06:59:01 debug Exp $
29 dpavlin 14 */
30    
31     #include <stdio.h>
32 dpavlin 42 #include <stdlib.h>
33 dpavlin 14
34 dpavlin 42
35 dpavlin 14 char *cond[16] = {
36     "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
37     "hi", "ls", "ge", "lt", "gt", "le", "", "" };
38    
39     int main(int argc, char *argv[])
40     {
41 dpavlin 42 int l, b, w=0, h, s, u=0, p=0, reg, c, n;
42     int only_array = 0;
43 dpavlin 14
44 dpavlin 42 if (argc == 1) {
45     only_array = 1;
46     } else {
47     if (argc != 4) {
48     fprintf(stderr, "puw missing?\n");
49     exit(1);
50     }
51     p = atoi(argv[1]);
52     u = atoi(argv[2]);
53     w = atoi(argv[3]);
54     }
55    
56 dpavlin 14 printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
57     printf("#include <stdio.h>\n#include <stdlib.h>\n"
58     "#include \"cpu.h\"\n"
59 dpavlin 18 "#include \"machine.h\"\n"
60 dpavlin 14 "#include \"memory.h\"\n"
61     "#include \"misc.h\"\n"
62 dpavlin 22 "#define DYNTRANS_PC_TO_POINTERS arm_pc_to_pointers\n"
63     "#include \"quick_pc_to_pointers.h\"\n"
64 dpavlin 14 "#define reg(x) (*((uint32_t *)(x)))\n");
65     printf("extern void arm_instr_nop(struct cpu *, "
66     "struct arm_instr_call *);\n");
67     printf("extern void arm_instr_invalid(struct cpu *, "
68     "struct arm_instr_call *);\n");
69 dpavlin 22 printf("extern void arm_pc_to_pointers(struct cpu *);\n");
70 dpavlin 14
71 dpavlin 42 if (!only_array)
72 dpavlin 14 for (reg=0; reg<=1; reg++)
73     for (b=0; b<=1; b++)
74     for (l=0; l<=1; l++) {
75     printf("#define A__NAME__general arm_instr_%s_"
76     "%s_%s_%s_%s_%s__general\n",
77     l?"load":"store", w? "w1" : "w0",
78     b? "byte" : "word", u? "u1" : "u0",
79     p? "p1" : "p0", reg? "reg" : "imm");
80    
81     printf("#define A__NAME arm_instr_%s_%s_%s_%s_%s_%s\n",
82     l? "load" : "store", w? "w1" : "w0",
83     b? "byte" : "word", u? "u1" : "u0",
84     p? "p1" : "p0", reg? "reg" : "imm");
85     for (c=0; c<14; c++)
86     printf("#define A__NAME__%s arm_instr_%s_"
87     "%s_%s_%s_%s_%s__%s\n",
88     cond[c], l?"load":"store", w? "w1" : "w0",
89     b? "byte" : "word", u? "u1" : "u0",
90     p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
91    
92     printf("#define A__NAME_PC arm_instr_%s_%s_%s_%s_"
93     "%s_%s_pc\n", l? "load" : "store", w? "w1" : "w0",
94     b? "byte" : "word", u? "u1" : "u0",
95     p? "p1" : "p0", reg? "reg" : "imm");
96     for (c=0; c<14; c++)
97     printf("#define A__NAME_PC__%s arm_instr_%s_"
98     "%s_%s_%s_%s_%s_pc__%s\n",
99     cond[c], l?"load":"store", w? "w1" : "w0",
100     b? "byte" : "word", u? "u1" : "u0",
101     p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
102    
103     if (l) printf("#define A__L\n");
104     if (w) printf("#define A__W\n");
105     if (b) printf("#define A__B\n");
106     if (u) printf("#define A__U\n");
107     if (p) printf("#define A__P\n");
108     if (reg)printf("#define A__REG\n");
109     printf("#include \"cpu_arm_instr_loadstore.c\"\n");
110     if (l) printf("#undef A__L\n");
111     if (w) printf("#undef A__W\n");
112     if (b) printf("#undef A__B\n");
113     if (u) printf("#undef A__U\n");
114     if (p) printf("#undef A__P\n");
115     if (reg)printf("#undef A__REG\n");
116     for (c=0; c<14; c++)
117     printf("#undef A__NAME__%s\n", cond[c]);
118     for (c=0; c<14; c++)
119     printf("#undef A__NAME_PC__%s\n", cond[c]);
120     printf("#undef A__NAME__general\n");
121     printf("#undef A__NAME_PC\n");
122     printf("#undef A__NAME\n");
123     }
124    
125 dpavlin 42 if (only_array) {
126     for (reg=0; reg<=1; reg++)
127     for (p=0; p<=1; p++)
128     for (u=0; u<=1; u++)
129     for (b=0; b<=1; b++)
130     for (w=0; w<=1; w++)
131     for (l=0; l<=1; l++)
132     for (c=0; c<16; c++) {
133     if (c == 15)
134     continue;
135    
136     printf("void arm_instr_%s_%s_%s"
137     "_%s_%s_%s%s%s(struct cpu *, struct "
138     "arm_instr_call *);",
139 dpavlin 14 l? "load" : "store",
140     w? "w1" : "w0",
141     b? "byte" : "word",
142     u? "u1" : "u0",
143     p? "p1" : "p0",
144     reg? "reg" : "imm",
145     c!=14? "__" : "", cond[c]);
146 dpavlin 42 printf("void arm_instr_%s_%s_%s_%s_%s_%s_pc%s%s"
147     "(struct cpu *, struct "
148     "arm_instr_call *);\n",
149 dpavlin 14 l? "load" : "store",
150     w? "w1" : "w0",
151     b? "byte" : "word",
152     u? "u1" : "u0",
153     p? "p1" : "p0",
154     reg? "reg" : "imm",
155     c!=14? "__" : "", cond[c]);
156 dpavlin 42 }
157 dpavlin 14
158 dpavlin 42 printf("\n\tvoid (*arm_load_store_instr[1024])(struct cpu *,\n"
159     "\t\tstruct arm_instr_call *) = {\n");
160     n = 0;
161     for (reg=0; reg<=1; reg++)
162     for (p=0; p<=1; p++)
163     for (u=0; u<=1; u++)
164     for (b=0; b<=1; b++)
165     for (w=0; w<=1; w++)
166     for (l=0; l<=1; l++)
167     for (c=0; c<16; c++) {
168     if (c == 15)
169     printf("\tarm_instr_nop");
170     else
171     printf("\tarm_instr_%s_%s_%s"
172     "_%s_%s_%s%s%s",
173     l? "load" : "store",
174     w? "w1" : "w0",
175     b? "byte" : "word",
176     u? "u1" : "u0",
177     p? "p1" : "p0",
178     reg? "reg" : "imm",
179     c!=14? "__" : "", cond[c]);
180     n++;
181     if (n!=2*2*2*2*2*2*16)
182     printf(",");
183     printf("\n");
184     }
185 dpavlin 14
186 dpavlin 42 printf("};\n\n");
187 dpavlin 14
188 dpavlin 42 /* Load/store with the pc register: */
189     printf("\n\tvoid (*arm_load_store_instr_pc[1024])"
190     "(struct cpu *,\n\t\tstruct arm_instr_call *) = {\n");
191     n = 0;
192     for (reg=0; reg<=1; reg++)
193     for (p=0; p<=1; p++)
194     for (u=0; u<=1; u++)
195     for (b=0; b<=1; b++)
196     for (w=0; w<=1; w++)
197     for (l=0; l<=1; l++)
198     for (c=0; c<16; c++) {
199     if (c == 15)
200     printf("\tarm_instr_nop");
201     else
202     printf("\tarm_instr_%s_%s_%s_"
203     "%s_%s_%s_pc%s%s",
204     l? "load" : "store",
205     w? "w1" : "w0",
206     b? "byte" : "word",
207     u? "u1" : "u0",
208     p? "p1" : "p0",
209     reg? "reg" : "imm",
210     c!=14? "__" : "", cond[c]);
211     n++;
212     if (n!=2*2*2*2*2*2*16)
213     printf(",");
214     printf("\n");
215     }
216 dpavlin 14
217 dpavlin 42 printf("};\n\n");
218     }
219    
220    
221 dpavlin 14 /* "Addressing mode 3": */
222    
223 dpavlin 42 if (!only_array)
224 dpavlin 14 for (reg=0; reg<=1; reg++)
225     for (h=0; h<=1; h++)
226     for (s=0; s<=1; s++)
227     for (l=0; l<=1; l++) {
228     if (s==0 && h==0)
229     continue;
230 dpavlin 22 /* l=0, s=1, h=0 means LDRD */
231 dpavlin 18 /* l=0, s=1, h=1 means STRD */
232 dpavlin 14
233     printf("#define A__NAME__general arm_instr_%s_"
234     "%s_%s_%s_%s_%s_%s__general\n",
235     l?"load":"store", w? "w1" : "w0",
236     s? "signed" : "unsigned",
237     h? "halfword" : "byte", u? "u1" : "u0",
238     p? "p1" : "p0", reg? "reg" : "imm");
239    
240     printf("#define A__NAME arm_instr_%s_%s_%s_%s_"
241     "%s_%s_%s\n", l? "load" : "store", w? "w1" : "w0",
242     s? "signed" : "unsigned",
243     h? "halfword" : "byte", u? "u1" : "u0",
244     p? "p1" : "p0", reg? "reg" : "imm");
245     for (c=0; c<14; c++)
246     printf("#define A__NAME__%s arm_instr_%s_"
247     "%s_%s_%s_%s_%s_%s__%s\n",
248     cond[c], l?"load":"store", w? "w1" : "w0",
249     s? "signed" : "unsigned",
250     h? "halfword" : "byte", u? "u1" : "u0",
251     p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
252    
253     printf("#define A__NAME_PC arm_instr_%s_%s_%s_%s_%s_"
254     "%s_%s_pc\n", l? "load" : "store", w? "w1" : "w0",
255     s? "signed" : "unsigned",
256     h? "halfword" : "byte", u? "u1" : "u0",
257     p? "p1" : "p0", reg? "reg" : "imm");
258     for (c=0; c<14; c++)
259     printf("#define A__NAME_PC__%s arm_instr_%s_"
260     "%s_%s_%s_%s_%s_%s_pc__%s\n",
261     cond[c], l?"load":"store", w? "w1" : "w0",
262     s? "signed" : "unsigned",
263     h? "halfword" : "byte", u? "u1" : "u0",
264     p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
265    
266     if (s) printf("#define A__SIGNED\n");
267     if (l) printf("#define A__L\n");
268     if (w) printf("#define A__W\n");
269     if (h) printf("#define A__H\n");
270     else printf("#define A__B\n");
271     if (u) printf("#define A__U\n");
272     if (p) printf("#define A__P\n");
273     if (reg)printf("#define A__REG\n");
274     printf("#include \"cpu_arm_instr_loadstore.c\"\n");
275     if (s) printf("#undef A__SIGNED\n");
276     if (l) printf("#undef A__L\n");
277     if (w) printf("#undef A__W\n");
278     if (h) printf("#undef A__H\n");
279     else printf("#undef A__B\n");
280     if (u) printf("#undef A__U\n");
281     if (p) printf("#undef A__P\n");
282     if (reg)printf("#undef A__REG\n");
283     for (c=0; c<14; c++)
284     printf("#undef A__NAME__%s\n", cond[c]);
285     for (c=0; c<14; c++)
286     printf("#undef A__NAME_PC__%s\n", cond[c]);
287     printf("#undef A__NAME__general\n");
288     printf("#undef A__NAME_PC\n");
289     printf("#undef A__NAME\n");
290     }
291    
292 dpavlin 42 if (only_array) {
293     for (reg=0; reg<=1; reg++)
294     for (p=0; p<=1; p++)
295     for (u=0; u<=1; u++)
296     for (h=0; h<=1; h++)
297     for (w=0; w<=1; w++)
298     for (s=0; s<=1; s++)
299     for (l=0; l<=1; l++)
300     for (c=0; c<16; c++) {
301     if (c == 15)
302     continue;
303     else if (s==0 && h==0)
304     continue;
305    
306     printf("void arm_instr_%s_%s_%s_%s_%s_%s_%s%s%s"
307     "(struct cpu *, struct arm_instr_call *);\n",
308 dpavlin 14 l? "load" : "store",
309     w? "w1" : "w0",
310     s? "signed" : "unsigned",
311     h? "halfword" : "byte",
312     u? "u1" : "u0", p? "p1" : "p0",
313     reg? "reg" : "imm",
314     c!=14? "__" : "", cond[c]);
315 dpavlin 42 printf("void arm_instr_%s_%s_%s_%s_%s_%s_"
316     "%s_pc%s%s(struct cpu *, struct "
317     "arm_instr_call *);\n",
318     l? "load" : "store",
319 dpavlin 14 w? "w1" : "w0",
320     s? "signed" : "unsigned",
321     h? "halfword" : "byte",
322     u? "u1" : "u0", p? "p1" : "p0",
323     reg? "reg" : "imm",
324     c!=14? "__" : "", cond[c]);
325 dpavlin 42 }
326 dpavlin 14
327 dpavlin 42 printf("\n\tvoid (*arm_load_store_instr_3[2048])"
328     "(struct cpu *,\n\t\tstruct arm_instr_call *) = {\n");
329     n = 0;
330     for (reg=0; reg<=1; reg++)
331     for (p=0; p<=1; p++)
332     for (u=0; u<=1; u++)
333     for (h=0; h<=1; h++)
334     for (w=0; w<=1; w++)
335     for (s=0; s<=1; s++)
336     for (l=0; l<=1; l++)
337     for (c=0; c<16; c++) {
338     if (c == 15)
339     printf("\tarm_instr_nop");
340     else if (s==0 && h==0)
341     printf("\tarm_instr_invalid");
342     else
343     printf("\tarm_instr_%s_%s_%s_%s_"
344     "%s_%s_%s%s%s",
345     l? "load" : "store",
346     w? "w1" : "w0",
347     s? "signed" : "unsigned",
348     h? "halfword" : "byte",
349     u? "u1" : "u0", p? "p1" : "p0",
350     reg? "reg" : "imm",
351     c!=14? "__" : "", cond[c]);
352     n++;
353     if (n!=2*2*2*2*2*2*2*16)
354     printf(",");
355     printf("\n");
356     }
357 dpavlin 14
358 dpavlin 42 printf("};\n\n");
359 dpavlin 14
360 dpavlin 42 /* Load/store with the pc register: */
361     printf("\n\tvoid (*arm_load_store_instr_3_pc[2048])"
362     "(struct cpu *,\n\t\tstruct arm_instr_call *) = {\n");
363     n = 0;
364     for (reg=0; reg<=1; reg++)
365     for (p=0; p<=1; p++)
366     for (u=0; u<=1; u++)
367     for (h=0; h<=1; h++)
368     for (w=0; w<=1; w++)
369     for (s=0; s<=1; s++)
370     for (l=0; l<=1; l++)
371     for (c=0; c<16; c++) {
372     if (c == 15)
373     printf("\tarm_instr_nop");
374     else if (s==0 && h==0)
375     printf("\tarm_instr_invalid");
376     else
377     printf("\tarm_instr_%s_%s_%s_%s_%s_%s_"
378     "%s_pc%s%s", l? "load" : "store",
379     w? "w1" : "w0",
380     s? "signed" : "unsigned",
381     h? "halfword" : "byte",
382     u? "u1" : "u0", p? "p1" : "p0",
383     reg? "reg" : "imm",
384     c!=14? "__" : "", cond[c]);
385     n++;
386     if (n!=2*2*2*2*2*2*2*16)
387     printf(",");
388     printf("\n");
389     }
390    
391     printf("};\n\n");
392     }
393    
394 dpavlin 14 return 0;
395     }
396    

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