/[gxemul]/trunk/src/cpus/generate_arm_loadstore.c
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Annotation of /trunk/src/cpus/generate_arm_loadstore.c

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Revision 18 - (hide annotations)
Mon Oct 8 16:19:11 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 10142 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============
1 dpavlin 14 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 18 * $Id: generate_arm_loadstore.c,v 1.4 2005/10/22 12:22:14 debug Exp $
29 dpavlin 14 */
30    
31     #include <stdio.h>
32    
33     char *cond[16] = {
34     "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
35     "hi", "ls", "ge", "lt", "gt", "le", "", "" };
36    
37     int main(int argc, char *argv[])
38     {
39     int l, b, w, h, s, u, p, reg, c, n;
40    
41     printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
42     printf("#include <stdio.h>\n#include <stdlib.h>\n"
43     "#include \"cpu.h\"\n"
44 dpavlin 18 "#include \"machine.h\"\n"
45 dpavlin 14 "#include \"memory.h\"\n"
46     "#include \"misc.h\"\n"
47 dpavlin 18 "#include \"arm_quick_pc_to_pointers.h\"\n"
48 dpavlin 14 "#define reg(x) (*((uint32_t *)(x)))\n");
49     printf("extern void arm_instr_nop(struct cpu *, "
50     "struct arm_instr_call *);\n");
51     printf("extern void arm_instr_invalid(struct cpu *, "
52     "struct arm_instr_call *);\n");
53    
54     for (reg=0; reg<=1; reg++)
55     for (p=0; p<=1; p++)
56     for (u=0; u<=1; u++)
57     for (b=0; b<=1; b++)
58     for (w=0; w<=1; w++)
59     for (l=0; l<=1; l++) {
60     printf("#define A__NAME__general arm_instr_%s_"
61     "%s_%s_%s_%s_%s__general\n",
62     l?"load":"store", w? "w1" : "w0",
63     b? "byte" : "word", u? "u1" : "u0",
64     p? "p1" : "p0", reg? "reg" : "imm");
65    
66     printf("#define A__NAME arm_instr_%s_%s_%s_%s_%s_%s\n",
67     l? "load" : "store", w? "w1" : "w0",
68     b? "byte" : "word", u? "u1" : "u0",
69     p? "p1" : "p0", reg? "reg" : "imm");
70     for (c=0; c<14; c++)
71     printf("#define A__NAME__%s arm_instr_%s_"
72     "%s_%s_%s_%s_%s__%s\n",
73     cond[c], l?"load":"store", w? "w1" : "w0",
74     b? "byte" : "word", u? "u1" : "u0",
75     p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
76    
77     printf("#define A__NAME_PC arm_instr_%s_%s_%s_%s_"
78     "%s_%s_pc\n", l? "load" : "store", w? "w1" : "w0",
79     b? "byte" : "word", u? "u1" : "u0",
80     p? "p1" : "p0", reg? "reg" : "imm");
81     for (c=0; c<14; c++)
82     printf("#define A__NAME_PC__%s arm_instr_%s_"
83     "%s_%s_%s_%s_%s_pc__%s\n",
84     cond[c], l?"load":"store", w? "w1" : "w0",
85     b? "byte" : "word", u? "u1" : "u0",
86     p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
87    
88     if (l) printf("#define A__L\n");
89     if (w) printf("#define A__W\n");
90     if (b) printf("#define A__B\n");
91     if (u) printf("#define A__U\n");
92     if (p) printf("#define A__P\n");
93     if (reg)printf("#define A__REG\n");
94     printf("#include \"cpu_arm_instr_loadstore.c\"\n");
95     if (l) printf("#undef A__L\n");
96     if (w) printf("#undef A__W\n");
97     if (b) printf("#undef A__B\n");
98     if (u) printf("#undef A__U\n");
99     if (p) printf("#undef A__P\n");
100     if (reg)printf("#undef A__REG\n");
101     for (c=0; c<14; c++)
102     printf("#undef A__NAME__%s\n", cond[c]);
103     for (c=0; c<14; c++)
104     printf("#undef A__NAME_PC__%s\n", cond[c]);
105     printf("#undef A__NAME__general\n");
106     printf("#undef A__NAME_PC\n");
107     printf("#undef A__NAME\n");
108     }
109    
110     printf("\n\tvoid (*arm_load_store_instr[1024])(struct cpu *,\n"
111     "\t\tstruct arm_instr_call *) = {\n");
112     n = 0;
113     for (reg=0; reg<=1; reg++)
114     for (p=0; p<=1; p++)
115     for (u=0; u<=1; u++)
116     for (b=0; b<=1; b++)
117     for (w=0; w<=1; w++)
118     for (l=0; l<=1; l++)
119     for (c=0; c<16; c++) {
120     if (c == 15)
121     printf("\tarm_instr_nop");
122     else
123     printf("\tarm_instr_%s_%s_%s_%s_%s_%s%s%s",
124     l? "load" : "store",
125     w? "w1" : "w0",
126     b? "byte" : "word",
127     u? "u1" : "u0",
128     p? "p1" : "p0",
129     reg? "reg" : "imm",
130     c!=14? "__" : "", cond[c]);
131     n++;
132     if (n!=2*2*2*2*2*2*16)
133     printf(",");
134     printf("\n");
135     }
136    
137     printf("};\n\n");
138    
139     /* Load/store with the pc register: */
140     printf("\n\tvoid (*arm_load_store_instr_pc[1024])(struct cpu *,\n"
141     "\t\tstruct arm_instr_call *) = {\n");
142     n = 0;
143     for (reg=0; reg<=1; reg++)
144     for (p=0; p<=1; p++)
145     for (u=0; u<=1; u++)
146     for (b=0; b<=1; b++)
147     for (w=0; w<=1; w++)
148     for (l=0; l<=1; l++)
149     for (c=0; c<16; c++) {
150     if (c == 15)
151     printf("\tarm_instr_nop");
152     else
153     printf("\tarm_instr_%s_%s_%s_%s_%s_%s_pc%s%s",
154     l? "load" : "store",
155     w? "w1" : "w0",
156     b? "byte" : "word",
157     u? "u1" : "u0",
158     p? "p1" : "p0",
159     reg? "reg" : "imm",
160     c!=14? "__" : "", cond[c]);
161     n++;
162     if (n!=2*2*2*2*2*2*16)
163     printf(",");
164     printf("\n");
165     }
166    
167     printf("};\n\n");
168    
169    
170    
171     /* "Addressing mode 3": */
172    
173     for (reg=0; reg<=1; reg++)
174     for (p=0; p<=1; p++)
175     for (u=0; u<=1; u++)
176     for (h=0; h<=1; h++)
177     for (w=0; w<=1; w++)
178     for (s=0; s<=1; s++)
179     for (l=0; l<=1; l++) {
180     if (s==0 && h==0)
181     continue;
182 dpavlin 18 if (l==0 && s==1 && h==0)
183 dpavlin 14 continue;
184 dpavlin 18 /* l=0, s=1, h=1 means STRD */
185 dpavlin 14
186     printf("#define A__NAME__general arm_instr_%s_"
187     "%s_%s_%s_%s_%s_%s__general\n",
188     l?"load":"store", w? "w1" : "w0",
189     s? "signed" : "unsigned",
190     h? "halfword" : "byte", u? "u1" : "u0",
191     p? "p1" : "p0", reg? "reg" : "imm");
192    
193     printf("#define A__NAME arm_instr_%s_%s_%s_%s_"
194     "%s_%s_%s\n", l? "load" : "store", w? "w1" : "w0",
195     s? "signed" : "unsigned",
196     h? "halfword" : "byte", u? "u1" : "u0",
197     p? "p1" : "p0", reg? "reg" : "imm");
198     for (c=0; c<14; c++)
199     printf("#define A__NAME__%s arm_instr_%s_"
200     "%s_%s_%s_%s_%s_%s__%s\n",
201     cond[c], l?"load":"store", w? "w1" : "w0",
202     s? "signed" : "unsigned",
203     h? "halfword" : "byte", u? "u1" : "u0",
204     p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
205    
206     printf("#define A__NAME_PC arm_instr_%s_%s_%s_%s_%s_"
207     "%s_%s_pc\n", l? "load" : "store", w? "w1" : "w0",
208     s? "signed" : "unsigned",
209     h? "halfword" : "byte", u? "u1" : "u0",
210     p? "p1" : "p0", reg? "reg" : "imm");
211     for (c=0; c<14; c++)
212     printf("#define A__NAME_PC__%s arm_instr_%s_"
213     "%s_%s_%s_%s_%s_%s_pc__%s\n",
214     cond[c], l?"load":"store", w? "w1" : "w0",
215     s? "signed" : "unsigned",
216     h? "halfword" : "byte", u? "u1" : "u0",
217     p? "p1" : "p0", reg? "reg" : "imm",cond[c]);
218    
219     if (s) printf("#define A__SIGNED\n");
220     if (l) printf("#define A__L\n");
221     if (w) printf("#define A__W\n");
222     if (h) printf("#define A__H\n");
223     else printf("#define A__B\n");
224     if (u) printf("#define A__U\n");
225     if (p) printf("#define A__P\n");
226     if (reg)printf("#define A__REG\n");
227     printf("#include \"cpu_arm_instr_loadstore.c\"\n");
228     if (s) printf("#undef A__SIGNED\n");
229     if (l) printf("#undef A__L\n");
230     if (w) printf("#undef A__W\n");
231     if (h) printf("#undef A__H\n");
232     else printf("#undef A__B\n");
233     if (u) printf("#undef A__U\n");
234     if (p) printf("#undef A__P\n");
235     if (reg)printf("#undef A__REG\n");
236     for (c=0; c<14; c++)
237     printf("#undef A__NAME__%s\n", cond[c]);
238     for (c=0; c<14; c++)
239     printf("#undef A__NAME_PC__%s\n", cond[c]);
240     printf("#undef A__NAME__general\n");
241     printf("#undef A__NAME_PC\n");
242     printf("#undef A__NAME\n");
243     }
244    
245     printf("\n\tvoid (*arm_load_store_instr_3[2048])(struct cpu *,\n"
246     "\t\tstruct arm_instr_call *) = {\n");
247     n = 0;
248     for (reg=0; reg<=1; reg++)
249     for (p=0; p<=1; p++)
250     for (u=0; u<=1; u++)
251     for (h=0; h<=1; h++)
252     for (w=0; w<=1; w++)
253     for (s=0; s<=1; s++)
254     for (l=0; l<=1; l++)
255     for (c=0; c<16; c++) {
256     if (c == 15)
257     printf("\tarm_instr_nop");
258     else if (s==0 && h==0)
259     printf("\tarm_instr_invalid");
260 dpavlin 18 else if (l==0 && s==1 && h==0)
261 dpavlin 14 printf("\tarm_instr_invalid");
262     else
263     printf("\tarm_instr_%s_%s_%s_%s_%s_%s_%s%s%s",
264     l? "load" : "store",
265     w? "w1" : "w0",
266     s? "signed" : "unsigned",
267     h? "halfword" : "byte",
268     u? "u1" : "u0", p? "p1" : "p0",
269     reg? "reg" : "imm",
270     c!=14? "__" : "", cond[c]);
271     n++;
272     if (n!=2*2*2*2*2*2*2*16)
273     printf(",");
274     printf("\n");
275     }
276    
277     printf("};\n\n");
278    
279     /* Load/store with the pc register: */
280     printf("\n\tvoid (*arm_load_store_instr_3_pc[2048])(struct cpu *,\n"
281     "\t\tstruct arm_instr_call *) = {\n");
282     n = 0;
283     for (reg=0; reg<=1; reg++)
284     for (p=0; p<=1; p++)
285     for (u=0; u<=1; u++)
286     for (h=0; h<=1; h++)
287     for (w=0; w<=1; w++)
288     for (s=0; s<=1; s++)
289     for (l=0; l<=1; l++)
290     for (c=0; c<16; c++) {
291     if (c == 15)
292     printf("\tarm_instr_nop");
293     else if (s==0 && h==0)
294     printf("\tarm_instr_invalid");
295 dpavlin 18 else if (l==0 && s==1 && h==0)
296 dpavlin 14 printf("\tarm_instr_invalid");
297     else
298     printf("\tarm_instr_%s_%s_%s_%s_%s_%s_"
299     "%s_pc%s%s", l? "load" : "store",
300     w? "w1" : "w0",
301     s? "signed" : "unsigned",
302     h? "halfword" : "byte",
303     u? "u1" : "u0", p? "p1" : "p0",
304     reg? "reg" : "imm",
305     c!=14? "__" : "", cond[c]);
306     n++;
307     if (n!=2*2*2*2*2*2*2*16)
308     printf(",");
309     printf("\n");
310     }
311    
312     printf("};\n\n");
313    
314    
315     return 0;
316     }
317    
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