/[gxemul]/trunk/src/cpus/generate_alpha_misc.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Annotation of /trunk/src/cpus/generate_alpha_misc.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (11 years, 11 months ago) by dpavlin
File MIME type: text/plain
File size: 11446 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 dpavlin 14 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: generate_alpha_misc.c,v 1.4 2006/12/30 13:30:55 debug Exp $
29 dpavlin 14 */
30    
31     #include <stdio.h>
32     #include <string.h>
33    
34    
35     char *sizechar[4] = { "b", "w", "l", "q" };
36    
37     #define N_CMPS 5
38     char *cmps[N_CMPS] = { "ult", "eq", "ule", "lt", "le" /*bge*/ };
39     #define N_CMOV 8
40     char *cmov[N_CMOV] = { "lbs", "lbc", "eq", "ne", "lt", "ge", "le", "gt" };
41    
42    
43     int main(int argc, char *argv[])
44     {
45 dpavlin 28 int load, size, zero, n, msk, llsc;
46 dpavlin 14 int ra, rc, lo, scale, imm, not, op, quad;
47    
48     printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
49    
50     n = 0;
51     /* add and sub: */
52     for (imm = 0; imm <= 1; imm ++)
53     for (quad = 0; quad <= 1; quad ++)
54     for (scale = 0; scale <= 8; scale += 4)
55     for (op = 0; op <= 1; op ++) {
56     printf("#define ALU_N alpha_instr_");
57     if (scale)
58     printf("s%i", scale);
59     printf("%s%s", op? "sub" : "add", quad? "q" : "l");
60     if (imm)
61     printf("_imm");
62     printf("\n");
63    
64     if (imm)
65     printf("#define ALU_IMM\n");
66     if (!quad)
67     printf("#define ALU_LONG\n");
68     if (op)
69     printf("#define ALU_SUB\n");
70     else
71     printf("#define ALU_ADD\n");
72     if (scale)
73     printf("#define ALU_S%i\n", scale);
74    
75     printf("#include \"cpu_alpha_instr_alu.c\"\n");
76    
77     if (imm)
78     printf("#undef ALU_IMM\n");
79     if (!quad)
80     printf("#undef ALU_LONG\n");
81     if (op)
82     printf("#undef ALU_SUB\n");
83     else
84     printf("#undef ALU_ADD\n");
85     if (scale)
86     printf("#undef ALU_S%i\n", scale);
87    
88     printf("#undef ALU_N\n");
89     }
90    
91     /* and, or, xor, zap, sll, srl, sra: */
92     for (imm = 0; imm <= 1; imm ++)
93     for (not = 0; not <= 1; not ++)
94     for (op = 0; op < 7; op ++) {
95     if (op >= 4 && not)
96     continue;
97     printf("#define ALU_N alpha_instr_");
98     switch (op) {
99     case 0: printf("and"); break;
100     case 1: printf("or"); break;
101     case 2: printf("xor"); break;
102     case 3: printf("zap"); break;
103     case 4: printf("sll"); break;
104     case 5: printf("srl"); break;
105     case 6: printf("sra"); break;
106     }
107     if (not)
108     printf("not");
109     if (imm)
110     printf("_imm");
111     printf("\n");
112     if (imm)
113     printf("#define ALU_IMM\n");
114     switch (op) {
115     case 0: printf("#define ALU_AND\n"); break;
116     case 1: printf("#define ALU_OR\n"); break;
117     case 2: printf("#define ALU_XOR\n"); break;
118     case 3: printf("#define ALU_ZAP\n"); break;
119     case 4: printf("#define ALU_SLL\n"); break;
120     case 5: printf("#define ALU_SRL\n"); break;
121     case 6: printf("#define ALU_SRA\n"); break;
122     }
123     if (not)
124     printf("#define ALU_NOT\n");
125     printf("#include \"cpu_alpha_instr_alu.c\"\n");
126    
127     if (imm)
128     printf("#undef ALU_IMM\n");
129     if (not)
130     printf("#undef ALU_NOT\n");
131     switch (op) {
132     case 0: printf("#undef ALU_AND\n"); break;
133     case 1: printf("#undef ALU_OR\n"); break;
134     case 2: printf("#undef ALU_XOR\n"); break;
135     case 3: printf("#undef ALU_ZAP\n"); break;
136     case 4: printf("#undef ALU_SLL\n"); break;
137     case 5: printf("#undef ALU_SRL\n"); break;
138     case 6: printf("#undef ALU_SRA\n"); break;
139     }
140    
141     printf("#undef ALU_N\n");
142     }
143    
144     printf("#define ALU_CMP\n");
145     for (imm = 0; imm <= 1; imm ++)
146     for (op = 0; op < N_CMPS; op ++) {
147     printf("#define ALU_N alpha_instr_cmp%s", cmps[op]);
148     if (imm)
149     printf("_imm");
150     printf("\n");
151    
152     if (imm)
153     printf("#define ALU_IMM\n");
154    
155     if (cmps[op][0] == 'u')
156     printf("#define ALU_UNSIGNED\n");
157     if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
158     printf("#define ALU_CMP_LT\n");
159     if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
160     printf("#define ALU_CMP_LE\n");
161     if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
162     printf("#define ALU_CMP_EQ\n");
163    
164     printf("#include \"cpu_alpha_instr_alu.c\"\n");
165    
166     if (cmps[op][0] == 'u')
167     printf("#undef ALU_UNSIGNED\n");
168     if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
169     printf("#undef ALU_CMP_LT\n");
170     if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
171     printf("#undef ALU_CMP_LE\n");
172     if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
173     printf("#undef ALU_CMP_EQ\n");
174     if (imm)
175     printf("#undef ALU_IMM\n");
176     printf("#undef ALU_N\n");
177     }
178     printf("#undef ALU_CMP\n");
179    
180     printf("#define ALU_CMOV\n");
181     for (imm = 0; imm <= 1; imm ++)
182     for (op = 0; op < N_CMOV; op ++) {
183     printf("#define ALU_N alpha_instr_cmov%s", cmov[op]);
184     if (imm)
185     printf("_imm");
186     printf("\n");
187     if (imm)
188     printf("#define ALU_IMM\n");
189     printf("#define ALU_CMOV_%s\n", cmov[op]);
190     printf("#include \"cpu_alpha_instr_alu.c\"\n");
191     printf("#undef ALU_CMOV_%s\n", cmov[op]);
192     if (imm)
193     printf("#undef ALU_IMM\n");
194     printf("#undef ALU_N\n");
195     }
196     printf("#undef ALU_CMOV\n");
197    
198 dpavlin 24 printf("#define ALU_CMPBGE\n");
199     for (imm = 0; imm <= 1; imm ++) {
200     printf("#define ALU_N alpha_instr_cmpbge");
201     if (imm)
202     printf("_imm");
203     printf("\n");
204     if (imm)
205     printf("#define ALU_IMM\n");
206     printf("#include \"cpu_alpha_instr_alu.c\"\n");
207     if (imm)
208     printf("#undef ALU_IMM\n");
209     printf("#undef ALU_N\n");
210     }
211     printf("#undef ALU_CMPBGE\n");
212    
213 dpavlin 14 for (imm = 0; imm <= 1; imm ++)
214     for (lo = 0; lo <= 1; lo ++)
215     for (msk = 0; msk <= 2; msk ++)
216     for (size=0; size<4; size++) {
217     if (size==0 && lo==0)
218     continue;
219     switch (msk) {
220     case 0: printf("#define ALU_MSK\n"); break;
221     case 1: printf("#define ALU_EXT\n"); break;
222     case 2: printf("#define ALU_INS\n"); break;
223     }
224     switch (msk) {
225     case 0: printf("#define ALU_N alpha_instr_msk"); break;
226     case 1: printf("#define ALU_N alpha_instr_ext"); break;
227     case 2: printf("#define ALU_N alpha_instr_ins"); break;
228     }
229     printf("%s", sizechar[size]);
230     if (lo)
231     printf("l");
232     else
233     printf("h");
234     if (imm)
235     printf("_imm");
236     printf("\n");
237     if (imm)
238     printf("#define ALU_IMM\n");
239     switch (size) {
240     case 0: printf("#define ALU_B\n"); break;
241     case 1: printf("#define ALU_W\n"); break;
242     case 2: printf("#define ALU_L\n"); break;
243     case 3: printf("#define ALU_Q\n"); break;
244     }
245     if (lo)
246     printf("#define ALU_LO\n");
247     printf("#include \"cpu_alpha_instr_alu.c\"\n");
248     switch (size) {
249     case 0: printf("#undef ALU_B\n"); break;
250     case 1: printf("#undef ALU_W\n"); break;
251     case 2: printf("#undef ALU_L\n"); break;
252     case 3: printf("#undef ALU_Q\n"); break;
253     }
254     switch (msk) {
255     case 0: printf("#undef ALU_MSK\n"); break;
256     case 1: printf("#undef ALU_EXT\n"); break;
257     case 2: printf("#undef ALU_INS\n"); break;
258     }
259     if (lo)
260     printf("#undef ALU_LO\n");
261     if (imm)
262     printf("#undef ALU_IMM\n");
263     printf("#undef ALU_N\n");
264     }
265    
266     /*
267     * Normal load/store:
268     */
269     for (llsc=0; llsc<=1; llsc++)
270     for (load=0; load<=1; load++)
271     for (zero=0; zero<=1; zero++)
272     for (size=0; size<4; size++) {
273     if (llsc && size < 2)
274     continue;
275     if (zero)
276     printf("#define LS_IGNORE_OFFSET\n");
277     if (load)
278     printf("#define LS_LOAD\n");
279     if (llsc)
280     printf("#define LS_LLSC\n");
281     switch (size) {
282     case 0: printf("#define LS_B\n"); break;
283     case 1: printf("#define LS_W\n"); break;
284     case 2: printf("#define LS_L\n"); break;
285     case 3: printf("#define LS_Q\n"); break;
286     }
287     printf("#define LS_GENERIC_N alpha_generic_");
288     if (load)
289     printf("ld");
290     else
291     printf("st");
292     printf("%s", sizechar[size]);
293     if (llsc)
294     printf("_llsc");
295     printf("\n");
296     printf("#define LS_N alpha_instr_");
297     if (load)
298     printf("ld");
299     else
300     printf("st");
301     printf("%s", sizechar[size]);
302     if (zero)
303     printf("_0");
304     if (llsc)
305     printf("_llsc");
306     printf("\n");
307     printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
308     printf("#undef LS_N\n");
309     printf("#undef LS_GENERIC_N\n");
310     switch (size) {
311     case 0: printf("#undef LS_B\n"); break;
312     case 1: printf("#undef LS_W\n"); break;
313     case 2: printf("#undef LS_L\n"); break;
314     case 3: printf("#undef LS_Q\n"); break;
315     }
316     if (load)
317     printf("#undef LS_LOAD\n");
318     if (llsc)
319     printf("#undef LS_LLSC\n");
320     if (zero)
321     printf("#undef LS_IGNORE_OFFSET\n");
322     }
323    
324     /*
325     * Unaligned load/store:
326     */
327     printf("#define LS_UNALIGNED\n");
328     for (load=0; load<=1; load++) {
329     size = 3;
330     if (load)
331     printf("#define LS_LOAD\n");
332     printf("#define LS_Q\n");
333     printf("#define LS_GENERIC_N alpha_generic_");
334     if (load)
335     printf("ld");
336     else
337     printf("st");
338     printf("%s", sizechar[size]);
339     printf("_u"); /* NOTE: unaligned */
340     printf("\n");
341     printf("#define LS_N alpha_instr_");
342     if (load)
343     printf("ld");
344     else
345     printf("st");
346     printf("%s", sizechar[size]);
347     printf("_u"); /* NOTE: unaligned */
348     printf("\n");
349     printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
350     printf("#undef LS_N\n");
351     printf("#undef LS_GENERIC_N\n");
352     printf("#undef LS_Q\n");
353     if (load)
354     printf("#undef LS_LOAD\n");
355     }
356     printf("#undef LS_UNALIGNED\n");
357    
358     /* Lookup table for most normal loads/stores: */
359 dpavlin 28 printf("\n\nvoid (*alpha_loadstore[32])(struct cpu *, struct "
360 dpavlin 14 "alpha_instr_call *) = {\n");
361    
362     for (llsc = 0; llsc <= 1; llsc ++)
363 dpavlin 28 for (load=0; load<=1; load++)
364     for (zero=0; zero<=1; zero++)
365 dpavlin 14 for (size=0; size<4; size++) {
366     printf("\talpha_instr_");
367     if (llsc && (size != 2 && size != 3)) {
368     printf("nop");
369     } else {
370     if (load)
371     printf("ld");
372     else
373     printf("st");
374     printf("%s", sizechar[size]);
375     if (zero)
376     printf("_0");
377     if (llsc)
378     printf("_llsc");
379     }
380     if (++n < 64)
381     printf(",");
382     printf("\n");
383     }
384    
385     printf("};\n\n");
386    
387     for (ra = 0; ra < 32; ra ++)
388     for (rc = 0; rc < 31; rc ++)
389     if (ra != rc) {
390     printf("static void alpha_instr_mov_%i_%i(struct cpu"
391     " *cpu, struct alpha_instr_call *ic)\n", ra, rc);
392     printf("{ cpu->cd.alpha.r[%i] = ", rc);
393     if (ra == 31)
394     printf("0");
395     else
396     printf("cpu->cd.alpha.r[%i]", ra);
397     printf("; }\n");
398     }
399    
400     printf("\n\nvoid (*alpha_mov_r_r[32*31])(struct cpu *, struct "
401     "alpha_instr_call *) = {\n");
402     n = 0;
403     for (rc = 0; rc < 31; rc ++)
404     for (ra = 0; ra < 32; ra ++) {
405     if (ra == rc)
406     printf("\talpha_instr_nop");
407     else
408     printf("\talpha_instr_mov_%i_%i", ra, rc);
409     if (++n < 31*32)
410     printf(",");
411     printf("\n");
412     }
413    
414     printf("};\n\n");
415    
416     return 0;
417     }
418    

  ViewVC Help
Powered by ViewVC 1.1.26