/[gxemul]/trunk/src/cpus/generate_alpha_misc.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/generate_alpha_misc.c

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 11767 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============
1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: generate_alpha_misc.c,v 1.2 2006/06/03 06:46:44 debug Exp $
29 */
30
31 #include <stdio.h>
32 #include <string.h>
33
34
35 char *sizechar[4] = { "b", "w", "l", "q" };
36
37 #define N_CMPS 5
38 char *cmps[N_CMPS] = { "ult", "eq", "ule", "lt", "le" /*bge*/ };
39 #define N_CMOV 8
40 char *cmov[N_CMOV] = { "lbs", "lbc", "eq", "ne", "lt", "ge", "le", "gt" };
41
42
43 int main(int argc, char *argv[])
44 {
45 int load, size, zero, aligncheck, n, msk, llsc;
46 int ra, rc, lo, scale, imm, not, op, quad;
47
48 printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
49
50 n = 0;
51 /* add and sub: */
52 for (imm = 0; imm <= 1; imm ++)
53 for (quad = 0; quad <= 1; quad ++)
54 for (scale = 0; scale <= 8; scale += 4)
55 for (op = 0; op <= 1; op ++) {
56 printf("#define ALU_N alpha_instr_");
57 if (scale)
58 printf("s%i", scale);
59 printf("%s%s", op? "sub" : "add", quad? "q" : "l");
60 if (imm)
61 printf("_imm");
62 printf("\n");
63
64 if (imm)
65 printf("#define ALU_IMM\n");
66 if (!quad)
67 printf("#define ALU_LONG\n");
68 if (op)
69 printf("#define ALU_SUB\n");
70 else
71 printf("#define ALU_ADD\n");
72 if (scale)
73 printf("#define ALU_S%i\n", scale);
74
75 printf("#include \"cpu_alpha_instr_alu.c\"\n");
76
77 if (imm)
78 printf("#undef ALU_IMM\n");
79 if (!quad)
80 printf("#undef ALU_LONG\n");
81 if (op)
82 printf("#undef ALU_SUB\n");
83 else
84 printf("#undef ALU_ADD\n");
85 if (scale)
86 printf("#undef ALU_S%i\n", scale);
87
88 printf("#undef ALU_N\n");
89 }
90
91 /* and, or, xor, zap, sll, srl, sra: */
92 for (imm = 0; imm <= 1; imm ++)
93 for (not = 0; not <= 1; not ++)
94 for (op = 0; op < 7; op ++) {
95 if (op >= 4 && not)
96 continue;
97 printf("#define ALU_N alpha_instr_");
98 switch (op) {
99 case 0: printf("and"); break;
100 case 1: printf("or"); break;
101 case 2: printf("xor"); break;
102 case 3: printf("zap"); break;
103 case 4: printf("sll"); break;
104 case 5: printf("srl"); break;
105 case 6: printf("sra"); break;
106 }
107 if (not)
108 printf("not");
109 if (imm)
110 printf("_imm");
111 printf("\n");
112 if (imm)
113 printf("#define ALU_IMM\n");
114 switch (op) {
115 case 0: printf("#define ALU_AND\n"); break;
116 case 1: printf("#define ALU_OR\n"); break;
117 case 2: printf("#define ALU_XOR\n"); break;
118 case 3: printf("#define ALU_ZAP\n"); break;
119 case 4: printf("#define ALU_SLL\n"); break;
120 case 5: printf("#define ALU_SRL\n"); break;
121 case 6: printf("#define ALU_SRA\n"); break;
122 }
123 if (not)
124 printf("#define ALU_NOT\n");
125 printf("#include \"cpu_alpha_instr_alu.c\"\n");
126
127 if (imm)
128 printf("#undef ALU_IMM\n");
129 if (not)
130 printf("#undef ALU_NOT\n");
131 switch (op) {
132 case 0: printf("#undef ALU_AND\n"); break;
133 case 1: printf("#undef ALU_OR\n"); break;
134 case 2: printf("#undef ALU_XOR\n"); break;
135 case 3: printf("#undef ALU_ZAP\n"); break;
136 case 4: printf("#undef ALU_SLL\n"); break;
137 case 5: printf("#undef ALU_SRL\n"); break;
138 case 6: printf("#undef ALU_SRA\n"); break;
139 }
140
141 printf("#undef ALU_N\n");
142 }
143
144 printf("#define ALU_CMP\n");
145 for (imm = 0; imm <= 1; imm ++)
146 for (op = 0; op < N_CMPS; op ++) {
147 printf("#define ALU_N alpha_instr_cmp%s", cmps[op]);
148 if (imm)
149 printf("_imm");
150 printf("\n");
151
152 if (imm)
153 printf("#define ALU_IMM\n");
154
155 if (cmps[op][0] == 'u')
156 printf("#define ALU_UNSIGNED\n");
157 if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
158 printf("#define ALU_CMP_LT\n");
159 if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
160 printf("#define ALU_CMP_LE\n");
161 if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
162 printf("#define ALU_CMP_EQ\n");
163
164 printf("#include \"cpu_alpha_instr_alu.c\"\n");
165
166 if (cmps[op][0] == 'u')
167 printf("#undef ALU_UNSIGNED\n");
168 if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
169 printf("#undef ALU_CMP_LT\n");
170 if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
171 printf("#undef ALU_CMP_LE\n");
172 if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
173 printf("#undef ALU_CMP_EQ\n");
174 if (imm)
175 printf("#undef ALU_IMM\n");
176 printf("#undef ALU_N\n");
177 }
178 printf("#undef ALU_CMP\n");
179
180 printf("#define ALU_CMOV\n");
181 for (imm = 0; imm <= 1; imm ++)
182 for (op = 0; op < N_CMOV; op ++) {
183 printf("#define ALU_N alpha_instr_cmov%s", cmov[op]);
184 if (imm)
185 printf("_imm");
186 printf("\n");
187 if (imm)
188 printf("#define ALU_IMM\n");
189 printf("#define ALU_CMOV_%s\n", cmov[op]);
190 printf("#include \"cpu_alpha_instr_alu.c\"\n");
191 printf("#undef ALU_CMOV_%s\n", cmov[op]);
192 if (imm)
193 printf("#undef ALU_IMM\n");
194 printf("#undef ALU_N\n");
195 }
196 printf("#undef ALU_CMOV\n");
197
198 printf("#define ALU_CMPBGE\n");
199 for (imm = 0; imm <= 1; imm ++) {
200 printf("#define ALU_N alpha_instr_cmpbge");
201 if (imm)
202 printf("_imm");
203 printf("\n");
204 if (imm)
205 printf("#define ALU_IMM\n");
206 printf("#include \"cpu_alpha_instr_alu.c\"\n");
207 if (imm)
208 printf("#undef ALU_IMM\n");
209 printf("#undef ALU_N\n");
210 }
211 printf("#undef ALU_CMPBGE\n");
212
213 for (imm = 0; imm <= 1; imm ++)
214 for (lo = 0; lo <= 1; lo ++)
215 for (msk = 0; msk <= 2; msk ++)
216 for (size=0; size<4; size++) {
217 if (size==0 && lo==0)
218 continue;
219 switch (msk) {
220 case 0: printf("#define ALU_MSK\n"); break;
221 case 1: printf("#define ALU_EXT\n"); break;
222 case 2: printf("#define ALU_INS\n"); break;
223 }
224 switch (msk) {
225 case 0: printf("#define ALU_N alpha_instr_msk"); break;
226 case 1: printf("#define ALU_N alpha_instr_ext"); break;
227 case 2: printf("#define ALU_N alpha_instr_ins"); break;
228 }
229 printf("%s", sizechar[size]);
230 if (lo)
231 printf("l");
232 else
233 printf("h");
234 if (imm)
235 printf("_imm");
236 printf("\n");
237 if (imm)
238 printf("#define ALU_IMM\n");
239 switch (size) {
240 case 0: printf("#define ALU_B\n"); break;
241 case 1: printf("#define ALU_W\n"); break;
242 case 2: printf("#define ALU_L\n"); break;
243 case 3: printf("#define ALU_Q\n"); break;
244 }
245 if (lo)
246 printf("#define ALU_LO\n");
247 printf("#include \"cpu_alpha_instr_alu.c\"\n");
248 switch (size) {
249 case 0: printf("#undef ALU_B\n"); break;
250 case 1: printf("#undef ALU_W\n"); break;
251 case 2: printf("#undef ALU_L\n"); break;
252 case 3: printf("#undef ALU_Q\n"); break;
253 }
254 switch (msk) {
255 case 0: printf("#undef ALU_MSK\n"); break;
256 case 1: printf("#undef ALU_EXT\n"); break;
257 case 2: printf("#undef ALU_INS\n"); break;
258 }
259 if (lo)
260 printf("#undef ALU_LO\n");
261 if (imm)
262 printf("#undef ALU_IMM\n");
263 printf("#undef ALU_N\n");
264 }
265
266 /*
267 * Normal load/store:
268 */
269 for (llsc=0; llsc<=1; llsc++)
270 for (aligncheck=0; aligncheck<=1; aligncheck++)
271 for (load=0; load<=1; load++)
272 for (zero=0; zero<=1; zero++)
273 for (size=0; size<4; size++) {
274 if (llsc && size < 2)
275 continue;
276 if (aligncheck)
277 printf("#define LS_ALIGN_CHECK\n");
278 if (zero)
279 printf("#define LS_IGNORE_OFFSET\n");
280 if (load)
281 printf("#define LS_LOAD\n");
282 if (llsc)
283 printf("#define LS_LLSC\n");
284 switch (size) {
285 case 0: printf("#define LS_B\n"); break;
286 case 1: printf("#define LS_W\n"); break;
287 case 2: printf("#define LS_L\n"); break;
288 case 3: printf("#define LS_Q\n"); break;
289 }
290 printf("#define LS_GENERIC_N alpha_generic_");
291 if (load)
292 printf("ld");
293 else
294 printf("st");
295 printf("%s", sizechar[size]);
296 if (llsc)
297 printf("_llsc");
298 printf("\n");
299 printf("#define LS_N alpha_instr_");
300 if (load)
301 printf("ld");
302 else
303 printf("st");
304 printf("%s", sizechar[size]);
305 if (zero)
306 printf("_0");
307 if (aligncheck)
308 printf("_aligncheck");
309 if (llsc)
310 printf("_llsc");
311 printf("\n");
312 printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
313 printf("#undef LS_N\n");
314 printf("#undef LS_GENERIC_N\n");
315 switch (size) {
316 case 0: printf("#undef LS_B\n"); break;
317 case 1: printf("#undef LS_W\n"); break;
318 case 2: printf("#undef LS_L\n"); break;
319 case 3: printf("#undef LS_Q\n"); break;
320 }
321 if (load)
322 printf("#undef LS_LOAD\n");
323 if (llsc)
324 printf("#undef LS_LLSC\n");
325 if (zero)
326 printf("#undef LS_IGNORE_OFFSET\n");
327 if (aligncheck)
328 printf("#undef LS_ALIGN_CHECK\n");
329 }
330
331 /*
332 * Unaligned load/store:
333 */
334 printf("#define LS_UNALIGNED\n");
335 for (load=0; load<=1; load++) {
336 size = 3;
337 if (load)
338 printf("#define LS_LOAD\n");
339 printf("#define LS_Q\n");
340 printf("#define LS_GENERIC_N alpha_generic_");
341 if (load)
342 printf("ld");
343 else
344 printf("st");
345 printf("%s", sizechar[size]);
346 printf("_u"); /* NOTE: unaligned */
347 printf("\n");
348 printf("#define LS_N alpha_instr_");
349 if (load)
350 printf("ld");
351 else
352 printf("st");
353 printf("%s", sizechar[size]);
354 printf("_u"); /* NOTE: unaligned */
355 printf("\n");
356 printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
357 printf("#undef LS_N\n");
358 printf("#undef LS_GENERIC_N\n");
359 printf("#undef LS_Q\n");
360 if (load)
361 printf("#undef LS_LOAD\n");
362 }
363 printf("#undef LS_UNALIGNED\n");
364
365 /* Lookup table for most normal loads/stores: */
366 printf("\n\nvoid (*alpha_loadstore[64])(struct cpu *, struct "
367 "alpha_instr_call *) = {\n");
368
369 for (llsc = 0; llsc <= 1; llsc ++)
370 for (aligncheck=0; aligncheck<=1; aligncheck++)
371 for (load=0; load<=1; load++)
372 for (zero=0; zero<=1; zero++)
373 for (size=0; size<4; size++) {
374 printf("\talpha_instr_");
375 if (llsc && (size != 2 && size != 3)) {
376 printf("nop");
377 } else {
378 if (load)
379 printf("ld");
380 else
381 printf("st");
382 printf("%s", sizechar[size]);
383 if (zero)
384 printf("_0");
385 if (aligncheck)
386 printf("_aligncheck");
387 if (llsc)
388 printf("_llsc");
389 }
390 if (++n < 64)
391 printf(",");
392 printf("\n");
393 }
394
395 printf("};\n\n");
396
397 for (ra = 0; ra < 32; ra ++)
398 for (rc = 0; rc < 31; rc ++)
399 if (ra != rc) {
400 printf("static void alpha_instr_mov_%i_%i(struct cpu"
401 " *cpu, struct alpha_instr_call *ic)\n", ra, rc);
402 printf("{ cpu->cd.alpha.r[%i] = ", rc);
403 if (ra == 31)
404 printf("0");
405 else
406 printf("cpu->cd.alpha.r[%i]", ra);
407 printf("; }\n");
408 }
409
410 printf("\n\nvoid (*alpha_mov_r_r[32*31])(struct cpu *, struct "
411 "alpha_instr_call *) = {\n");
412 n = 0;
413 for (rc = 0; rc < 31; rc ++)
414 for (ra = 0; ra < 32; ra ++) {
415 if (ra == rc)
416 printf("\talpha_instr_nop");
417 else
418 printf("\talpha_instr_mov_%i_%i", ra, rc);
419 if (++n < 31*32)
420 printf(",");
421 printf("\n");
422 }
423
424 printf("};\n\n");
425
426 return 0;
427 }
428
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