/[gxemul]/trunk/src/cpus/generate_alpha_misc.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/generate_alpha_misc.c

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Revision 14 - (show annotations)
Mon Oct 8 16:18:51 2007 UTC (14 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 11404 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: generate_alpha_misc.c,v 1.1 2005/08/29 14:36:41 debug Exp $
29 */
30
31 #include <stdio.h>
32 #include <string.h>
33
34
35 char *sizechar[4] = { "b", "w", "l", "q" };
36
37 #define N_CMPS 5
38 char *cmps[N_CMPS] = { "ult", "eq", "ule", "lt", "le" /*bge*/ };
39 #define N_CMOV 8
40 char *cmov[N_CMOV] = { "lbs", "lbc", "eq", "ne", "lt", "ge", "le", "gt" };
41
42
43 int main(int argc, char *argv[])
44 {
45 int load, size, zero, aligncheck, n, msk, llsc;
46 int ra, rc, lo, scale, imm, not, op, quad;
47
48 printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
49
50 n = 0;
51 /* add and sub: */
52 for (imm = 0; imm <= 1; imm ++)
53 for (quad = 0; quad <= 1; quad ++)
54 for (scale = 0; scale <= 8; scale += 4)
55 for (op = 0; op <= 1; op ++) {
56 printf("#define ALU_N alpha_instr_");
57 if (scale)
58 printf("s%i", scale);
59 printf("%s%s", op? "sub" : "add", quad? "q" : "l");
60 if (imm)
61 printf("_imm");
62 printf("\n");
63
64 if (imm)
65 printf("#define ALU_IMM\n");
66 if (!quad)
67 printf("#define ALU_LONG\n");
68 if (op)
69 printf("#define ALU_SUB\n");
70 else
71 printf("#define ALU_ADD\n");
72 if (scale)
73 printf("#define ALU_S%i\n", scale);
74
75 printf("#include \"cpu_alpha_instr_alu.c\"\n");
76
77 if (imm)
78 printf("#undef ALU_IMM\n");
79 if (!quad)
80 printf("#undef ALU_LONG\n");
81 if (op)
82 printf("#undef ALU_SUB\n");
83 else
84 printf("#undef ALU_ADD\n");
85 if (scale)
86 printf("#undef ALU_S%i\n", scale);
87
88 printf("#undef ALU_N\n");
89 }
90
91 /* and, or, xor, zap, sll, srl, sra: */
92 for (imm = 0; imm <= 1; imm ++)
93 for (not = 0; not <= 1; not ++)
94 for (op = 0; op < 7; op ++) {
95 if (op >= 4 && not)
96 continue;
97 printf("#define ALU_N alpha_instr_");
98 switch (op) {
99 case 0: printf("and"); break;
100 case 1: printf("or"); break;
101 case 2: printf("xor"); break;
102 case 3: printf("zap"); break;
103 case 4: printf("sll"); break;
104 case 5: printf("srl"); break;
105 case 6: printf("sra"); break;
106 }
107 if (not)
108 printf("not");
109 if (imm)
110 printf("_imm");
111 printf("\n");
112 if (imm)
113 printf("#define ALU_IMM\n");
114 switch (op) {
115 case 0: printf("#define ALU_AND\n"); break;
116 case 1: printf("#define ALU_OR\n"); break;
117 case 2: printf("#define ALU_XOR\n"); break;
118 case 3: printf("#define ALU_ZAP\n"); break;
119 case 4: printf("#define ALU_SLL\n"); break;
120 case 5: printf("#define ALU_SRL\n"); break;
121 case 6: printf("#define ALU_SRA\n"); break;
122 }
123 if (not)
124 printf("#define ALU_NOT\n");
125 printf("#include \"cpu_alpha_instr_alu.c\"\n");
126
127 if (imm)
128 printf("#undef ALU_IMM\n");
129 if (not)
130 printf("#undef ALU_NOT\n");
131 switch (op) {
132 case 0: printf("#undef ALU_AND\n"); break;
133 case 1: printf("#undef ALU_OR\n"); break;
134 case 2: printf("#undef ALU_XOR\n"); break;
135 case 3: printf("#undef ALU_ZAP\n"); break;
136 case 4: printf("#undef ALU_SLL\n"); break;
137 case 5: printf("#undef ALU_SRL\n"); break;
138 case 6: printf("#undef ALU_SRA\n"); break;
139 }
140
141 printf("#undef ALU_N\n");
142 }
143
144 printf("#define ALU_CMP\n");
145 for (imm = 0; imm <= 1; imm ++)
146 for (op = 0; op < N_CMPS; op ++) {
147 printf("#define ALU_N alpha_instr_cmp%s", cmps[op]);
148 if (imm)
149 printf("_imm");
150 printf("\n");
151
152 if (imm)
153 printf("#define ALU_IMM\n");
154
155 if (cmps[op][0] == 'u')
156 printf("#define ALU_UNSIGNED\n");
157 if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
158 printf("#define ALU_CMP_LT\n");
159 if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
160 printf("#define ALU_CMP_LE\n");
161 if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
162 printf("#define ALU_CMP_EQ\n");
163
164 printf("#include \"cpu_alpha_instr_alu.c\"\n");
165
166 if (cmps[op][0] == 'u')
167 printf("#undef ALU_UNSIGNED\n");
168 if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
169 printf("#undef ALU_CMP_LT\n");
170 if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
171 printf("#undef ALU_CMP_LE\n");
172 if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
173 printf("#undef ALU_CMP_EQ\n");
174 if (imm)
175 printf("#undef ALU_IMM\n");
176 printf("#undef ALU_N\n");
177 }
178 printf("#undef ALU_CMP\n");
179
180 printf("#define ALU_CMOV\n");
181 for (imm = 0; imm <= 1; imm ++)
182 for (op = 0; op < N_CMOV; op ++) {
183 printf("#define ALU_N alpha_instr_cmov%s", cmov[op]);
184 if (imm)
185 printf("_imm");
186 printf("\n");
187 if (imm)
188 printf("#define ALU_IMM\n");
189 printf("#define ALU_CMOV_%s\n", cmov[op]);
190 printf("#include \"cpu_alpha_instr_alu.c\"\n");
191 printf("#undef ALU_CMOV_%s\n", cmov[op]);
192 if (imm)
193 printf("#undef ALU_IMM\n");
194 printf("#undef ALU_N\n");
195 }
196 printf("#undef ALU_CMOV\n");
197
198 for (imm = 0; imm <= 1; imm ++)
199 for (lo = 0; lo <= 1; lo ++)
200 for (msk = 0; msk <= 2; msk ++)
201 for (size=0; size<4; size++) {
202 if (size==0 && lo==0)
203 continue;
204 switch (msk) {
205 case 0: printf("#define ALU_MSK\n"); break;
206 case 1: printf("#define ALU_EXT\n"); break;
207 case 2: printf("#define ALU_INS\n"); break;
208 }
209 switch (msk) {
210 case 0: printf("#define ALU_N alpha_instr_msk"); break;
211 case 1: printf("#define ALU_N alpha_instr_ext"); break;
212 case 2: printf("#define ALU_N alpha_instr_ins"); break;
213 }
214 printf("%s", sizechar[size]);
215 if (lo)
216 printf("l");
217 else
218 printf("h");
219 if (imm)
220 printf("_imm");
221 printf("\n");
222 if (imm)
223 printf("#define ALU_IMM\n");
224 switch (size) {
225 case 0: printf("#define ALU_B\n"); break;
226 case 1: printf("#define ALU_W\n"); break;
227 case 2: printf("#define ALU_L\n"); break;
228 case 3: printf("#define ALU_Q\n"); break;
229 }
230 if (lo)
231 printf("#define ALU_LO\n");
232 printf("#include \"cpu_alpha_instr_alu.c\"\n");
233 switch (size) {
234 case 0: printf("#undef ALU_B\n"); break;
235 case 1: printf("#undef ALU_W\n"); break;
236 case 2: printf("#undef ALU_L\n"); break;
237 case 3: printf("#undef ALU_Q\n"); break;
238 }
239 switch (msk) {
240 case 0: printf("#undef ALU_MSK\n"); break;
241 case 1: printf("#undef ALU_EXT\n"); break;
242 case 2: printf("#undef ALU_INS\n"); break;
243 }
244 if (lo)
245 printf("#undef ALU_LO\n");
246 if (imm)
247 printf("#undef ALU_IMM\n");
248 printf("#undef ALU_N\n");
249 }
250
251 /*
252 * Normal load/store:
253 */
254 for (llsc=0; llsc<=1; llsc++)
255 for (aligncheck=0; aligncheck<=1; aligncheck++)
256 for (load=0; load<=1; load++)
257 for (zero=0; zero<=1; zero++)
258 for (size=0; size<4; size++) {
259 if (llsc && size < 2)
260 continue;
261 if (aligncheck)
262 printf("#define LS_ALIGN_CHECK\n");
263 if (zero)
264 printf("#define LS_IGNORE_OFFSET\n");
265 if (load)
266 printf("#define LS_LOAD\n");
267 if (llsc)
268 printf("#define LS_LLSC\n");
269 switch (size) {
270 case 0: printf("#define LS_B\n"); break;
271 case 1: printf("#define LS_W\n"); break;
272 case 2: printf("#define LS_L\n"); break;
273 case 3: printf("#define LS_Q\n"); break;
274 }
275 printf("#define LS_GENERIC_N alpha_generic_");
276 if (load)
277 printf("ld");
278 else
279 printf("st");
280 printf("%s", sizechar[size]);
281 if (llsc)
282 printf("_llsc");
283 printf("\n");
284 printf("#define LS_N alpha_instr_");
285 if (load)
286 printf("ld");
287 else
288 printf("st");
289 printf("%s", sizechar[size]);
290 if (zero)
291 printf("_0");
292 if (aligncheck)
293 printf("_aligncheck");
294 if (llsc)
295 printf("_llsc");
296 printf("\n");
297 printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
298 printf("#undef LS_N\n");
299 printf("#undef LS_GENERIC_N\n");
300 switch (size) {
301 case 0: printf("#undef LS_B\n"); break;
302 case 1: printf("#undef LS_W\n"); break;
303 case 2: printf("#undef LS_L\n"); break;
304 case 3: printf("#undef LS_Q\n"); break;
305 }
306 if (load)
307 printf("#undef LS_LOAD\n");
308 if (llsc)
309 printf("#undef LS_LLSC\n");
310 if (zero)
311 printf("#undef LS_IGNORE_OFFSET\n");
312 if (aligncheck)
313 printf("#undef LS_ALIGN_CHECK\n");
314 }
315
316 /*
317 * Unaligned load/store:
318 */
319 printf("#define LS_UNALIGNED\n");
320 for (load=0; load<=1; load++) {
321 size = 3;
322 if (load)
323 printf("#define LS_LOAD\n");
324 printf("#define LS_Q\n");
325 printf("#define LS_GENERIC_N alpha_generic_");
326 if (load)
327 printf("ld");
328 else
329 printf("st");
330 printf("%s", sizechar[size]);
331 printf("_u"); /* NOTE: unaligned */
332 printf("\n");
333 printf("#define LS_N alpha_instr_");
334 if (load)
335 printf("ld");
336 else
337 printf("st");
338 printf("%s", sizechar[size]);
339 printf("_u"); /* NOTE: unaligned */
340 printf("\n");
341 printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
342 printf("#undef LS_N\n");
343 printf("#undef LS_GENERIC_N\n");
344 printf("#undef LS_Q\n");
345 if (load)
346 printf("#undef LS_LOAD\n");
347 }
348 printf("#undef LS_UNALIGNED\n");
349
350 /* Lookup table for most normal loads/stores: */
351 printf("\n\nvoid (*alpha_loadstore[64])(struct cpu *, struct "
352 "alpha_instr_call *) = {\n");
353
354 for (llsc = 0; llsc <= 1; llsc ++)
355 for (aligncheck=0; aligncheck<=1; aligncheck++)
356 for (load=0; load<=1; load++)
357 for (zero=0; zero<=1; zero++)
358 for (size=0; size<4; size++) {
359 printf("\talpha_instr_");
360 if (llsc && (size != 2 && size != 3)) {
361 printf("nop");
362 } else {
363 if (load)
364 printf("ld");
365 else
366 printf("st");
367 printf("%s", sizechar[size]);
368 if (zero)
369 printf("_0");
370 if (aligncheck)
371 printf("_aligncheck");
372 if (llsc)
373 printf("_llsc");
374 }
375 if (++n < 64)
376 printf(",");
377 printf("\n");
378 }
379
380 printf("};\n\n");
381
382 for (ra = 0; ra < 32; ra ++)
383 for (rc = 0; rc < 31; rc ++)
384 if (ra != rc) {
385 printf("static void alpha_instr_mov_%i_%i(struct cpu"
386 " *cpu, struct alpha_instr_call *ic)\n", ra, rc);
387 printf("{ cpu->cd.alpha.r[%i] = ", rc);
388 if (ra == 31)
389 printf("0");
390 else
391 printf("cpu->cd.alpha.r[%i]", ra);
392 printf("; }\n");
393 }
394
395 printf("\n\nvoid (*alpha_mov_r_r[32*31])(struct cpu *, struct "
396 "alpha_instr_call *) = {\n");
397 n = 0;
398 for (rc = 0; rc < 31; rc ++)
399 for (ra = 0; ra < 32; ra ++) {
400 if (ra == rc)
401 printf("\talpha_instr_nop");
402 else
403 printf("\talpha_instr_mov_%i_%i", ra, rc);
404 if (++n < 31*32)
405 printf(",");
406 printf("\n");
407 }
408
409 printf("};\n\n");
410
411 return 0;
412 }
413

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