/[gxemul]/trunk/src/cpus/generate_alpha_misc.c
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Annotation of /trunk/src/cpus/generate_alpha_misc.c

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 2 months ago) by dpavlin
File MIME type: text/plain
File size: 11446 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 dpavlin 14 /*
2 dpavlin 28 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 28 * $Id: generate_alpha_misc.c,v 1.3 2006/06/30 20:22:54 debug Exp $
29 dpavlin 14 */
30    
31     #include <stdio.h>
32     #include <string.h>
33    
34    
35     char *sizechar[4] = { "b", "w", "l", "q" };
36    
37     #define N_CMPS 5
38     char *cmps[N_CMPS] = { "ult", "eq", "ule", "lt", "le" /*bge*/ };
39     #define N_CMOV 8
40     char *cmov[N_CMOV] = { "lbs", "lbc", "eq", "ne", "lt", "ge", "le", "gt" };
41    
42    
43     int main(int argc, char *argv[])
44     {
45 dpavlin 28 int load, size, zero, n, msk, llsc;
46 dpavlin 14 int ra, rc, lo, scale, imm, not, op, quad;
47    
48     printf("\n/* AUTOMATICALLY GENERATED! Do not edit. */\n\n");
49    
50     n = 0;
51     /* add and sub: */
52     for (imm = 0; imm <= 1; imm ++)
53     for (quad = 0; quad <= 1; quad ++)
54     for (scale = 0; scale <= 8; scale += 4)
55     for (op = 0; op <= 1; op ++) {
56     printf("#define ALU_N alpha_instr_");
57     if (scale)
58     printf("s%i", scale);
59     printf("%s%s", op? "sub" : "add", quad? "q" : "l");
60     if (imm)
61     printf("_imm");
62     printf("\n");
63    
64     if (imm)
65     printf("#define ALU_IMM\n");
66     if (!quad)
67     printf("#define ALU_LONG\n");
68     if (op)
69     printf("#define ALU_SUB\n");
70     else
71     printf("#define ALU_ADD\n");
72     if (scale)
73     printf("#define ALU_S%i\n", scale);
74    
75     printf("#include \"cpu_alpha_instr_alu.c\"\n");
76    
77     if (imm)
78     printf("#undef ALU_IMM\n");
79     if (!quad)
80     printf("#undef ALU_LONG\n");
81     if (op)
82     printf("#undef ALU_SUB\n");
83     else
84     printf("#undef ALU_ADD\n");
85     if (scale)
86     printf("#undef ALU_S%i\n", scale);
87    
88     printf("#undef ALU_N\n");
89     }
90    
91     /* and, or, xor, zap, sll, srl, sra: */
92     for (imm = 0; imm <= 1; imm ++)
93     for (not = 0; not <= 1; not ++)
94     for (op = 0; op < 7; op ++) {
95     if (op >= 4 && not)
96     continue;
97     printf("#define ALU_N alpha_instr_");
98     switch (op) {
99     case 0: printf("and"); break;
100     case 1: printf("or"); break;
101     case 2: printf("xor"); break;
102     case 3: printf("zap"); break;
103     case 4: printf("sll"); break;
104     case 5: printf("srl"); break;
105     case 6: printf("sra"); break;
106     }
107     if (not)
108     printf("not");
109     if (imm)
110     printf("_imm");
111     printf("\n");
112     if (imm)
113     printf("#define ALU_IMM\n");
114     switch (op) {
115     case 0: printf("#define ALU_AND\n"); break;
116     case 1: printf("#define ALU_OR\n"); break;
117     case 2: printf("#define ALU_XOR\n"); break;
118     case 3: printf("#define ALU_ZAP\n"); break;
119     case 4: printf("#define ALU_SLL\n"); break;
120     case 5: printf("#define ALU_SRL\n"); break;
121     case 6: printf("#define ALU_SRA\n"); break;
122     }
123     if (not)
124     printf("#define ALU_NOT\n");
125     printf("#include \"cpu_alpha_instr_alu.c\"\n");
126    
127     if (imm)
128     printf("#undef ALU_IMM\n");
129     if (not)
130     printf("#undef ALU_NOT\n");
131     switch (op) {
132     case 0: printf("#undef ALU_AND\n"); break;
133     case 1: printf("#undef ALU_OR\n"); break;
134     case 2: printf("#undef ALU_XOR\n"); break;
135     case 3: printf("#undef ALU_ZAP\n"); break;
136     case 4: printf("#undef ALU_SLL\n"); break;
137     case 5: printf("#undef ALU_SRL\n"); break;
138     case 6: printf("#undef ALU_SRA\n"); break;
139     }
140    
141     printf("#undef ALU_N\n");
142     }
143    
144     printf("#define ALU_CMP\n");
145     for (imm = 0; imm <= 1; imm ++)
146     for (op = 0; op < N_CMPS; op ++) {
147     printf("#define ALU_N alpha_instr_cmp%s", cmps[op]);
148     if (imm)
149     printf("_imm");
150     printf("\n");
151    
152     if (imm)
153     printf("#define ALU_IMM\n");
154    
155     if (cmps[op][0] == 'u')
156     printf("#define ALU_UNSIGNED\n");
157     if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
158     printf("#define ALU_CMP_LT\n");
159     if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
160     printf("#define ALU_CMP_LE\n");
161     if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
162     printf("#define ALU_CMP_EQ\n");
163    
164     printf("#include \"cpu_alpha_instr_alu.c\"\n");
165    
166     if (cmps[op][0] == 'u')
167     printf("#undef ALU_UNSIGNED\n");
168     if (strcmp(cmps[op]+strlen(cmps[op])-2,"lt") == 0)
169     printf("#undef ALU_CMP_LT\n");
170     if (strcmp(cmps[op]+strlen(cmps[op])-2,"le") == 0)
171     printf("#undef ALU_CMP_LE\n");
172     if (strcmp(cmps[op]+strlen(cmps[op])-2,"eq") == 0)
173     printf("#undef ALU_CMP_EQ\n");
174     if (imm)
175     printf("#undef ALU_IMM\n");
176     printf("#undef ALU_N\n");
177     }
178     printf("#undef ALU_CMP\n");
179    
180     printf("#define ALU_CMOV\n");
181     for (imm = 0; imm <= 1; imm ++)
182     for (op = 0; op < N_CMOV; op ++) {
183     printf("#define ALU_N alpha_instr_cmov%s", cmov[op]);
184     if (imm)
185     printf("_imm");
186     printf("\n");
187     if (imm)
188     printf("#define ALU_IMM\n");
189     printf("#define ALU_CMOV_%s\n", cmov[op]);
190     printf("#include \"cpu_alpha_instr_alu.c\"\n");
191     printf("#undef ALU_CMOV_%s\n", cmov[op]);
192     if (imm)
193     printf("#undef ALU_IMM\n");
194     printf("#undef ALU_N\n");
195     }
196     printf("#undef ALU_CMOV\n");
197    
198 dpavlin 24 printf("#define ALU_CMPBGE\n");
199     for (imm = 0; imm <= 1; imm ++) {
200     printf("#define ALU_N alpha_instr_cmpbge");
201     if (imm)
202     printf("_imm");
203     printf("\n");
204     if (imm)
205     printf("#define ALU_IMM\n");
206     printf("#include \"cpu_alpha_instr_alu.c\"\n");
207     if (imm)
208     printf("#undef ALU_IMM\n");
209     printf("#undef ALU_N\n");
210     }
211     printf("#undef ALU_CMPBGE\n");
212    
213 dpavlin 14 for (imm = 0; imm <= 1; imm ++)
214     for (lo = 0; lo <= 1; lo ++)
215     for (msk = 0; msk <= 2; msk ++)
216     for (size=0; size<4; size++) {
217     if (size==0 && lo==0)
218     continue;
219     switch (msk) {
220     case 0: printf("#define ALU_MSK\n"); break;
221     case 1: printf("#define ALU_EXT\n"); break;
222     case 2: printf("#define ALU_INS\n"); break;
223     }
224     switch (msk) {
225     case 0: printf("#define ALU_N alpha_instr_msk"); break;
226     case 1: printf("#define ALU_N alpha_instr_ext"); break;
227     case 2: printf("#define ALU_N alpha_instr_ins"); break;
228     }
229     printf("%s", sizechar[size]);
230     if (lo)
231     printf("l");
232     else
233     printf("h");
234     if (imm)
235     printf("_imm");
236     printf("\n");
237     if (imm)
238     printf("#define ALU_IMM\n");
239     switch (size) {
240     case 0: printf("#define ALU_B\n"); break;
241     case 1: printf("#define ALU_W\n"); break;
242     case 2: printf("#define ALU_L\n"); break;
243     case 3: printf("#define ALU_Q\n"); break;
244     }
245     if (lo)
246     printf("#define ALU_LO\n");
247     printf("#include \"cpu_alpha_instr_alu.c\"\n");
248     switch (size) {
249     case 0: printf("#undef ALU_B\n"); break;
250     case 1: printf("#undef ALU_W\n"); break;
251     case 2: printf("#undef ALU_L\n"); break;
252     case 3: printf("#undef ALU_Q\n"); break;
253     }
254     switch (msk) {
255     case 0: printf("#undef ALU_MSK\n"); break;
256     case 1: printf("#undef ALU_EXT\n"); break;
257     case 2: printf("#undef ALU_INS\n"); break;
258     }
259     if (lo)
260     printf("#undef ALU_LO\n");
261     if (imm)
262     printf("#undef ALU_IMM\n");
263     printf("#undef ALU_N\n");
264     }
265    
266     /*
267     * Normal load/store:
268     */
269     for (llsc=0; llsc<=1; llsc++)
270     for (load=0; load<=1; load++)
271     for (zero=0; zero<=1; zero++)
272     for (size=0; size<4; size++) {
273     if (llsc && size < 2)
274     continue;
275     if (zero)
276     printf("#define LS_IGNORE_OFFSET\n");
277     if (load)
278     printf("#define LS_LOAD\n");
279     if (llsc)
280     printf("#define LS_LLSC\n");
281     switch (size) {
282     case 0: printf("#define LS_B\n"); break;
283     case 1: printf("#define LS_W\n"); break;
284     case 2: printf("#define LS_L\n"); break;
285     case 3: printf("#define LS_Q\n"); break;
286     }
287     printf("#define LS_GENERIC_N alpha_generic_");
288     if (load)
289     printf("ld");
290     else
291     printf("st");
292     printf("%s", sizechar[size]);
293     if (llsc)
294     printf("_llsc");
295     printf("\n");
296     printf("#define LS_N alpha_instr_");
297     if (load)
298     printf("ld");
299     else
300     printf("st");
301     printf("%s", sizechar[size]);
302     if (zero)
303     printf("_0");
304     if (llsc)
305     printf("_llsc");
306     printf("\n");
307     printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
308     printf("#undef LS_N\n");
309     printf("#undef LS_GENERIC_N\n");
310     switch (size) {
311     case 0: printf("#undef LS_B\n"); break;
312     case 1: printf("#undef LS_W\n"); break;
313     case 2: printf("#undef LS_L\n"); break;
314     case 3: printf("#undef LS_Q\n"); break;
315     }
316     if (load)
317     printf("#undef LS_LOAD\n");
318     if (llsc)
319     printf("#undef LS_LLSC\n");
320     if (zero)
321     printf("#undef LS_IGNORE_OFFSET\n");
322     }
323    
324     /*
325     * Unaligned load/store:
326     */
327     printf("#define LS_UNALIGNED\n");
328     for (load=0; load<=1; load++) {
329     size = 3;
330     if (load)
331     printf("#define LS_LOAD\n");
332     printf("#define LS_Q\n");
333     printf("#define LS_GENERIC_N alpha_generic_");
334     if (load)
335     printf("ld");
336     else
337     printf("st");
338     printf("%s", sizechar[size]);
339     printf("_u"); /* NOTE: unaligned */
340     printf("\n");
341     printf("#define LS_N alpha_instr_");
342     if (load)
343     printf("ld");
344     else
345     printf("st");
346     printf("%s", sizechar[size]);
347     printf("_u"); /* NOTE: unaligned */
348     printf("\n");
349     printf("#include \"cpu_alpha_instr_loadstore.c\"\n");
350     printf("#undef LS_N\n");
351     printf("#undef LS_GENERIC_N\n");
352     printf("#undef LS_Q\n");
353     if (load)
354     printf("#undef LS_LOAD\n");
355     }
356     printf("#undef LS_UNALIGNED\n");
357    
358     /* Lookup table for most normal loads/stores: */
359 dpavlin 28 printf("\n\nvoid (*alpha_loadstore[32])(struct cpu *, struct "
360 dpavlin 14 "alpha_instr_call *) = {\n");
361    
362     for (llsc = 0; llsc <= 1; llsc ++)
363 dpavlin 28 for (load=0; load<=1; load++)
364     for (zero=0; zero<=1; zero++)
365 dpavlin 14 for (size=0; size<4; size++) {
366     printf("\talpha_instr_");
367     if (llsc && (size != 2 && size != 3)) {
368     printf("nop");
369     } else {
370     if (load)
371     printf("ld");
372     else
373     printf("st");
374     printf("%s", sizechar[size]);
375     if (zero)
376     printf("_0");
377     if (llsc)
378     printf("_llsc");
379     }
380     if (++n < 64)
381     printf(",");
382     printf("\n");
383     }
384    
385     printf("};\n\n");
386    
387     for (ra = 0; ra < 32; ra ++)
388     for (rc = 0; rc < 31; rc ++)
389     if (ra != rc) {
390     printf("static void alpha_instr_mov_%i_%i(struct cpu"
391     " *cpu, struct alpha_instr_call *ic)\n", ra, rc);
392     printf("{ cpu->cd.alpha.r[%i] = ", rc);
393     if (ra == 31)
394     printf("0");
395     else
396     printf("cpu->cd.alpha.r[%i]", ra);
397     printf("; }\n");
398     }
399    
400     printf("\n\nvoid (*alpha_mov_r_r[32*31])(struct cpu *, struct "
401     "alpha_instr_call *) = {\n");
402     n = 0;
403     for (rc = 0; rc < 31; rc ++)
404     for (ra = 0; ra < 32; ra ++) {
405     if (ra == rc)
406     printf("\talpha_instr_nop");
407     else
408     printf("\talpha_instr_mov_%i_%i", ra, rc);
409     if (++n < 31*32)
410     printf(",");
411     printf("\n");
412     }
413    
414     printf("};\n\n");
415    
416     return 0;
417     }
418    

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