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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_x86.c,v 1.3 2005/09/30 14:17:03 debug Exp $ |
* $Id: cpu_x86.c,v 1.18 2006/09/23 03:49:02 debug Exp $ |
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* |
* |
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* x86 (and amd64) CPU emulation. |
* x86 (and amd64) CPU emulation. |
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* |
* |
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* |
* |
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* TODO: Pretty much everything that has to do with 64-bit and 32-bit modes, |
* NOTE: I ripped out pretty much everything that had to do with x86 |
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* memory translation, flag bits, and so on. |
* emulation, when doing the transition to dyntrans. This CPU mode |
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* hasn't been rewritten yet. |
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* |
* |
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* See http://www.amd.com/us-en/Processors/DevelopWithAMD/ |
* Right now, it is completely bogus. |
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* 0,,30_2252_875_7044,00.html for more info on AMD64. |
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* |
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* http://www.cs.ucla.edu/~kohler/class/04f-aos/ref/i386/appa.htm has a |
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* nice overview of the standard i386 opcodes. |
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* |
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* HelpPC (http://members.tripod.com/~oldboard/assembly/) is also useful. |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "settings.h" |
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#include "symbol.h" |
#include "symbol.h" |
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#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
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/* #define DYNTRANS_32 */ |
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#define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
#define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
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#include "tmp_x86_head.c" |
#include "tmp_x86_head.c" |
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cpu->cd.x86.model = models[i]; |
cpu->cd.x86.model = models[i]; |
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cpu->translate_v2p = x86_translate_v2p; |
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/* Initial startup is in 16-bit real mode: */ |
/* Initial startup is in 16-bit real mode: */ |
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cpu->pc = 0xfff0; |
cpu->pc = 0xfff0; |
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cpu->cd.x86.descr_cache[X86_S_CS].writable = 1; |
cpu->cd.x86.descr_cache[X86_S_CS].writable = 1; |
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cpu->cd.x86.descr_cache[X86_S_CS].granularity = 0; |
cpu->cd.x86.descr_cache[X86_S_CS].granularity = 0; |
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cpu->cd.x86.s[X86_S_CS] = 0xf000; |
cpu->cd.x86.s[X86_S_CS] = 0xf000; |
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cpu->cd.x86.cursegment = X86_S_CS; |
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cpu->cd.x86.idtr = 0; |
cpu->cd.x86.idtr = 0; |
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cpu->cd.x86.idtr_limit = 0x3ff; |
cpu->cd.x86.idtr_limit = 0x3ff; |
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cpu->translate_address = x86_translate_address; |
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cpu->cd.x86.rflags = 0x0002; |
cpu->cd.x86.rflags = 0x0002; |
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if (cpu->cd.x86.model.model_number == X86_MODEL_8086) |
if (cpu->cd.x86.model.model_number == X86_MODEL_8086) |
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cpu->cd.x86.rflags |= 0xf000; |
cpu->cd.x86.rflags |= 0xf000; |
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cpu->is_32bit = (cpu->cd.x86.model.model_number < X86_MODEL_AMD64)? |
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1 : 0; |
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if (cpu->is_32bit) { |
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cpu->run_instr = x8632_run_instr; |
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cpu->update_translation_table = x8632_update_translation_table; |
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cpu->invalidate_translation_caches = |
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x8632_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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x8632_invalidate_code_translation; |
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} else { |
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cpu->run_instr = x86_run_instr; |
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cpu->update_translation_table = x86_update_translation_table; |
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cpu->invalidate_translation_caches = |
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x86_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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x86_invalidate_code_translation; |
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} |
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
if (cpu_id == 0) { |
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debug("%s", cpu->name); |
debug("%s", cpu->name); |
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} |
} |
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/* |
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* Add all register names to the settings: |
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* |
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* Note that the name 'pc' is also added. It equals 64-bit RIP. |
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*/ |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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/* TODO: All of the following: */ |
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#if 0 |
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if (strcasecmp(name, "pc") == 0 || strcasecmp(name, "rip") == 0) { |
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if (strcasecmp(name, "ip") == 0) { |
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if (strcasecmp(name, "eip") == 0) { |
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if (strcasecmp(name, "rflags") == 0) { |
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if (strcasecmp(name, "eflags") == 0) { |
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if (strcasecmp(name, "flags") == 0) { |
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/* 8-bit low */ |
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if (strcasecmp(name, reg_names_bytes[r]) == 0) { |
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/* 8-bit high: */ |
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for (r=0; r<4; r++) |
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if (strcasecmp(name, reg_names_bytes[r+4]) == 0) { |
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/* 16-, 32-, 64-bit registers: */ |
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for (r=0; r<N_X86_REGS; r++) { |
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if (r<8 && strcasecmp(name, reg_names[r]) == 0) { |
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/* 32-bit: */ |
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if (r<8 && (name[0]=='e' || name[0]=='E') && |
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/* 64-bit: */ |
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if ((name[0]=='r' || name[0]=='R') && |
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strcasecmp(name+1, reg_names[r]) == 0) { |
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/* segment names: */ |
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for (r=0; r<N_X86_SEGS; r++) { |
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if (strcasecmp(name, seg_names[r]) == 0) { |
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/* control registers: (TODO: 32- vs 64-bit on AMD64?) */ |
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if (strncasecmp(name, "cr", 2) == 0 && atoi(name+2) < N_X86_CREGS ) { |
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#endif |
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return 1; |
return 1; |
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} |
} |
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while (models[i].model_number != 0) { |
while (models[i].model_number != 0) { |
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debug("%s", models[i].name); |
debug("%s", models[i].name); |
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for (j=0; j<10-strlen(models[i].name); j++) |
for (j=0; j<10-(int)strlen(models[i].name); j++) |
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debug(" "); |
debug(" "); |
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i++; |
i++; |
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if ((i % 6) == 0 || models[i].name == NULL) |
if ((i % 6) == 0 || models[i].name == NULL) |
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uint64_t offset; |
uint64_t offset; |
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int i, x = cpu->cpu_id; |
int i, x = cpu->cpu_id; |
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if (REAL_MODE) { |
if (LONG_MODE) { |
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/* Real-mode: */ |
/* 64-bit long mode: */ |
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debug("cpu%i: cs:ip = 0x%04x:0x%04x\n", x, |
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cpu->cd.x86.s[X86_S_CS], (int)cpu->pc); |
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debug("cpu%i: ax = 0x%04x bx = 0x%04x cx = 0x%04x dx = " |
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"0x%04x\n", x, |
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(int)cpu->cd.x86.r[X86_R_AX], (int)cpu->cd.x86.r[X86_R_BX], |
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(int)cpu->cd.x86.r[X86_R_CX], (int)cpu->cd.x86.r[X86_R_DX]); |
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debug("cpu%i: si = 0x%04x di = 0x%04x bp = 0x%04x sp = " |
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"0x%04x\n", x, |
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(int)cpu->cd.x86.r[X86_R_SI], (int)cpu->cd.x86.r[X86_R_DI], |
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(int)cpu->cd.x86.r[X86_R_BP], (int)cpu->cd.x86.r[X86_R_SP]); |
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debug("cpu%i: ds = 0x%04x es = 0x%04x ss = 0x%04x flags " |
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"= 0x%04x\n", x, |
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(int)cpu->cd.x86.s[X86_S_DS], (int)cpu->cd.x86.s[X86_S_ES], |
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(int)cpu->cd.x86.s[X86_S_SS], (int)cpu->cd.x86.rflags); |
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} else { |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
cpu->pc, &offset); |
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debug("cpu%i: eip=0x", x); |
debug("cpu%i: rip = 0x%016"PRIx64, x, cpu->pc); |
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debug("%08x", (int)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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debug("cpu%i: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=" |
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"0x%08x\n", x, |
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(int)cpu->cd.x86.r[X86_R_AX], (int)cpu->cd.x86.r[X86_R_BX], |
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(int)cpu->cd.x86.r[X86_R_CX], (int)cpu->cd.x86.r[X86_R_DX]); |
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debug("cpu%i: esi=0x%08x edi=0x%08x ebp=0x%08x esp=" |
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"0x%08x\n", x, |
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(int)cpu->cd.x86.r[X86_R_SI], (int)cpu->cd.x86.r[X86_R_DI], |
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(int)cpu->cd.x86.r[X86_R_BP], (int)cpu->cd.x86.r[X86_R_SP]); |
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#if 0 |
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} else { |
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/* 64-bit */ |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i: rip = 0x", x); |
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debug("%016llx", (long long)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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for (i=0; i<N_X86_REGS; i++) { |
for (i=0; i<N_X86_REGS; i++) { |
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if ((i & 1) == 0) |
if ((i & 1) == 0) |
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debug("cpu%i:", x); |
debug("cpu%i:", x); |
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debug(" r%s = 0x%016llx", reg_names[i], |
debug(" r%s = 0x%016"PRIx64, reg_names[i], |
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(long long)cpu->cd.x86.r[i]); |
(uint64_t)cpu->cd.x86.r[i]); |
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if ((i & 1) == 1) |
if ((i & 1) == 1) |
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debug("\n"); |
debug("\n"); |
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} |
} |
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#endif |
} else if (REAL_MODE) { |
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/* 16-bit real-mode: */ |
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debug("cpu%i: cs:ip = 0x%04"PRIx16":0x%04"PRIx16"\n", x, |
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cpu->cd.x86.s[X86_S_CS], (uint16_t)cpu->pc); |
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debug("cpu%i: ax = 0x%04"PRIx16" bx = 0x%04"PRIx16 |
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" cx = 0x%04"PRIx16" dx = 0x%04"PRIx16"\n", x, |
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(uint16_t)cpu->cd.x86.r[X86_R_AX], |
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(uint16_t)cpu->cd.x86.r[X86_R_BX], |
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(uint16_t)cpu->cd.x86.r[X86_R_CX], |
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(uint16_t)cpu->cd.x86.r[X86_R_DX]); |
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debug("cpu%i: si = 0x%04"PRIx16" di = 0x%04"PRIx16 |
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" bp = 0x%04"PRIx16" sp = 0x%04"PRIx16"\n", x, |
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(uint16_t)cpu->cd.x86.r[X86_R_SI], |
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(uint16_t)cpu->cd.x86.r[X86_R_DI], |
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(uint16_t)cpu->cd.x86.r[X86_R_BP], |
257 |
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(uint16_t)cpu->cd.x86.r[X86_R_SP]); |
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debug("cpu%i: ds = 0x%04"PRIx16" es = 0x%04"PRIx16 |
259 |
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" ss = 0x%04"PRIx16" flags = 0x%04"PRIx16"\n", x, |
260 |
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(uint16_t)cpu->cd.x86.s[X86_S_DS], |
261 |
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(uint16_t)cpu->cd.x86.s[X86_S_ES], |
262 |
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(uint16_t)cpu->cd.x86.s[X86_S_SS], |
263 |
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(uint16_t)cpu->cd.x86.rflags); |
264 |
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} else { |
265 |
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/* 32-bit protected mode: */ |
266 |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
267 |
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cpu->pc, &offset); |
268 |
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269 |
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debug("cpu%i: eip=0x%08"PRIx32, x, (uint32_t)cpu->pc); |
270 |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
271 |
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272 |
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debug("cpu%i: eax=0x%08"PRIx32" ebx=0x%08"PRIx32 |
273 |
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" ecx=0x%08"PRIx32" edx=0x%08"PRIx32"\n", x, |
274 |
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(uint32_t)cpu->cd.x86.r[X86_R_AX], |
275 |
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(uint32_t)cpu->cd.x86.r[X86_R_BX], |
276 |
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(uint32_t)cpu->cd.x86.r[X86_R_CX], |
277 |
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(uint32_t)cpu->cd.x86.r[X86_R_DX]); |
278 |
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debug("cpu%i: esi=0x%08"PRIx32" edi=0x%08"PRIx32 |
279 |
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" ebp=0x%08"PRIx32" esp=0x%08"PRIx32"\n", x, |
280 |
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(uint32_t)cpu->cd.x86.r[X86_R_SI], |
281 |
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(uint32_t)cpu->cd.x86.r[X86_R_DI], |
282 |
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(uint32_t)cpu->cd.x86.r[X86_R_BP], |
283 |
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(uint32_t)cpu->cd.x86.r[X86_R_SP]); |
284 |
} |
} |
285 |
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286 |
if (coprocs != 0) { |
if (coprocs != 0) { |
319 |
cpu->machine->isa_pic_data.pic2->irq_base); |
cpu->machine->isa_pic_data.pic2->irq_base); |
320 |
} else if (PROTECTED_MODE) { |
} else if (PROTECTED_MODE) { |
321 |
/* Protected mode: */ |
/* Protected mode: */ |
322 |
debug("cpu%i: cs=0x%04x ds=0x%04x es=0x%04x " |
debug("cpu%i: cs=0x%04"PRIx16" ds=0x%04"PRIx16" es=0x%04" |
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"fs=0x%04x gs=0x%04x ss=0x%04x\n", x, |
PRIx16" fs=0x%04"PRIx16" gs=0x%04"PRIx16" ss=0x%04" |
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(int)cpu->cd.x86.s[X86_S_CS], (int)cpu->cd.x86.s[X86_S_DS], |
PRIx16"\n", x, (uint16_t)cpu->cd.x86.s[X86_S_CS], |
325 |
(int)cpu->cd.x86.s[X86_S_ES], (int)cpu->cd.x86.s[X86_S_FS], |
(uint16_t)cpu->cd.x86.s[X86_S_DS], |
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(int)cpu->cd.x86.s[X86_S_GS], (int)cpu->cd.x86.s[X86_S_SS]); |
(uint16_t)cpu->cd.x86.s[X86_S_ES], |
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(uint16_t)cpu->cd.x86.s[X86_S_FS], |
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(uint16_t)cpu->cd.x86.s[X86_S_GS], |
329 |
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(uint16_t)cpu->cd.x86.s[X86_S_SS]); |
330 |
} |
} |
331 |
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332 |
if (PROTECTED_MODE) { |
if (PROTECTED_MODE) { |
333 |
/* Protected mode: */ |
/* Protected mode: */ |
334 |
debug("cpu%i: cr0=0x%08x cr2=0x%08x cr3=0x%08x eflags=" |
debug("cpu%i: cr0=0x%08"PRIx32" cr2=0x%08"PRIx32" cr3=0x%08" |
335 |
"0x%08x\n", x, (int)cpu->cd.x86.cr[0], |
PRIx32" eflags=0x%08"PRIx32"\n", x, |
336 |
(int)cpu->cd.x86.cr[2], (int)cpu->cd.x86.cr[3], |
(uint32_t)cpu->cd.x86.cr[0], (uint32_t)cpu->cd.x86.cr[2], |
337 |
(int)cpu->cd.x86.rflags); |
(uint32_t)cpu->cd.x86.cr[3], (uint32_t)cpu->cd.x86.rflags); |
338 |
debug("cpu%i: tr = 0x%04x (base=0x%llx, limit=0x%x)\n", |
debug("cpu%i: tr = 0x%04"PRIx16" (base=0x%"PRIx64", limit=0x" |
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x, (int)cpu->cd.x86.tr, (long long)cpu->cd.x86.tr_base, |
PRIx32")\n", x, (uint16_t)cpu->cd.x86.tr, (uint64_t) |
340 |
(int)cpu->cd.x86.tr_limit); |
cpu->cd.x86.tr_base, (uint32_t)cpu->cd.x86.tr_limit); |
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} |
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} |
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/* |
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* x86_cpu_register_match(): |
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*/ |
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void x86_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *mr) |
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{ |
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int cpunr = 0; |
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int r; |
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/* CPU number: TODO */ |
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if (strcasecmp(name, "pc") == 0 || strcasecmp(name, "rip") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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m->cpus[cpunr]->cd.x86.halted = 0; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*mr = 1; |
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return; |
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} |
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if (strcasecmp(name, "ip") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = (m->cpus[cpunr]->pc & ~0xffff) |
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| (*valuep & 0xffff); |
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m->cpus[cpunr]->cd.x86.halted = 0; |
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} else |
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*valuep = m->cpus[cpunr]->pc & 0xffff; |
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*mr = 1; |
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return; |
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} |
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if (strcasecmp(name, "eip") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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m->cpus[cpunr]->cd.x86.halted = 0; |
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} else |
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*valuep = m->cpus[cpunr]->pc & 0xffffffffULL; |
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*mr = 1; |
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return; |
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} |
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if (strcasecmp(name, "rflags") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.x86.rflags = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.x86.rflags; |
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*mr = 1; |
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return; |
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} |
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if (strcasecmp(name, "eflags") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.x86.rflags = (m->cpus[cpunr]-> |
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cd.x86.rflags & ~0xffffffffULL) | (*valuep & |
|
|
0xffffffffULL); |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.x86.rflags & 0xffffffffULL; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
|
if (strcasecmp(name, "flags") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.x86.rflags = (m->cpus[cpunr]-> |
|
|
cd.x86.rflags & ~0xffff) | (*valuep & 0xffff); |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.x86.rflags & 0xffff; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
|
|
|
|
/* 8-bit low: */ |
|
|
for (r=0; r<4; r++) |
|
|
if (strcasecmp(name, reg_names_bytes[r]) == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.x86.r[r] = |
|
|
(m->cpus[cpunr]->cd.x86.r[r] & ~0xff) |
|
|
| (*valuep & 0xff); |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.x86.r[r] & 0xff; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
|
|
|
|
/* 8-bit high: */ |
|
|
for (r=0; r<4; r++) |
|
|
if (strcasecmp(name, reg_names_bytes[r+4]) == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.x86.r[r] = |
|
|
(m->cpus[cpunr]->cd.x86.r[r] & ~0xff00) |
|
|
| ((*valuep & 0xff) << 8); |
|
|
else |
|
|
*valuep = (m->cpus[cpunr]->cd.x86.r[r] >> |
|
|
8) & 0xff; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
|
|
|
|
/* 16-, 32-, 64-bit registers: */ |
|
|
for (r=0; r<N_X86_REGS; r++) { |
|
|
/* 16-bit: */ |
|
|
if (r<8 && strcasecmp(name, reg_names[r]) == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.x86.r[r] = |
|
|
(m->cpus[cpunr]->cd.x86.r[r] & ~0xffff) |
|
|
| (*valuep & 0xffff); |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.x86.r[r] & 0xffff; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
|
|
|
|
/* 32-bit: */ |
|
|
if (r<8 && (name[0]=='e' || name[0]=='E') && |
|
|
strcasecmp(name+1, reg_names[r]) == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.x86.r[r] = |
|
|
*valuep & 0xffffffffULL; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.x86.r[r] & |
|
|
0xffffffffULL; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
|
|
|
|
/* 64-bit: */ |
|
|
if ((name[0]=='r' || name[0]=='R') && |
|
|
strcasecmp(name+1, reg_names[r]) == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.x86.r[r] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.x86.r[r]; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
|
} |
|
|
|
|
|
/* segment names: */ |
|
|
for (r=0; r<N_X86_SEGS; r++) { |
|
|
if (strcasecmp(name, seg_names[r]) == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.x86.s[r] = |
|
|
(m->cpus[cpunr]->cd.x86.s[r] & ~0xffff) |
|
|
| (*valuep & 0xffff); |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.x86.s[r] & 0xffff; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
341 |
} |
} |
|
|
|
|
/* control registers: (TODO: 32- vs 64-bit on AMD64?) */ |
|
|
if (strncasecmp(name, "cr", 2) == 0 && atoi(name+2) < N_X86_CREGS ) { |
|
|
int r = atoi(name+2); |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.x86.cr[r] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.x86.cr[r]; |
|
|
*mr = 1; |
|
|
return; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* x86_cpu_show_full_statistics(): |
|
|
* |
|
|
* Show detailed statistics on opcode usage on each cpu. |
|
|
*/ |
|
|
void x86_cpu_show_full_statistics(struct machine *m) |
|
|
{ |
|
|
fatal("x86_cpu_show_full_statistics(): TODO\n"); |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* x86_cpu_tlbdump(): |
|
|
* |
|
|
* Called from the debugger to dump the TLB in a readable format. |
|
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
|
|
* |
|
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
|
|
* just dumped. |
|
|
*/ |
|
|
void x86_cpu_tlbdump(struct machine *m, int x, int rawflag) |
|
|
{ |
|
|
fatal("ppc_cpu_tlbdump(): TODO\n"); |
|
342 |
} |
} |
343 |
|
|
344 |
|
|
389 |
} |
} |
390 |
|
|
391 |
|
|
392 |
static uint32_t read_imm(unsigned char **instrp, uint64_t *newpcp, |
uint32_t read_imm(unsigned char **instrp, uint64_t *newpcp, |
393 |
int mode) |
int mode) |
394 |
{ |
{ |
395 |
return read_imm_common(instrp, newpcp, mode, 0); |
return read_imm_common(instrp, newpcp, mode, 0); |
396 |
} |
} |
397 |
|
|
398 |
|
|
399 |
static void print_csip(struct cpu *cpu) |
void print_csip(struct cpu *cpu) |
400 |
{ |
{ |
401 |
fatal("0x%04x:", cpu->cd.x86.s[X86_S_CS]); |
fatal("0x%04x:", cpu->cd.x86.s[X86_S_CS]); |
402 |
if (PROTECTED_MODE) |
if (PROTECTED_MODE) |
407 |
|
|
408 |
|
|
409 |
/* |
/* |
410 |
|
* x86_cpu_tlbdump(): |
411 |
|
* |
412 |
|
* Called from the debugger to dump the TLB in a readable format. |
413 |
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
414 |
|
* |
415 |
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
416 |
|
* just dumped. |
417 |
|
*/ |
418 |
|
void x86_cpu_tlbdump(struct machine *m, int x, int rawflag) |
419 |
|
{ |
420 |
|
} |
421 |
|
|
422 |
|
|
423 |
|
/* |
424 |
|
* x86_cpu_gdb_stub(): |
425 |
|
* |
426 |
|
* Execute a "remote GDB" command. Returns a newly allocated response string |
427 |
|
* on success, NULL on failure. |
428 |
|
*/ |
429 |
|
char *x86_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
430 |
|
{ |
431 |
|
fatal("x86_cpu_gdb_stub(): TODO\n"); |
432 |
|
return NULL; |
433 |
|
} |
434 |
|
|
435 |
|
|
436 |
|
/* |
437 |
* x86_cpu_interrupt(): |
* x86_cpu_interrupt(): |
438 |
* |
* |
439 |
* NOTE: Interacting with the 8259 PIC is done in src/machine.c. |
* NOTE: Interacting with the 8259 PIC is done in src/machine.c. |
563 |
reload_segment_descriptor(cpu, RELOAD_TR, new_tr, NULL); |
reload_segment_descriptor(cpu, RELOAD_TR, new_tr, NULL); |
564 |
|
|
565 |
if (cpu->cd.x86.tr_limit < 0x67) |
if (cpu->cd.x86.tr_limit < 0x67) |
566 |
fatal("WARNING: tr_limit = 0x%x, must be at least 0x67!\n", |
fatal("WARNING: tr_limit = 0x%"PRIx16", must be at least " |
567 |
(int)cpu->cd.x86.tr_limit); |
"0x67!\n", (uint16_t)cpu->cd.x86.tr_limit); |
568 |
|
|
569 |
/* Read new registers: */ |
/* Read new registers: */ |
570 |
#define READ_VALUE { cpu->memory_rw(cpu, cpu->mem, cpu->cd.x86.tr_base + \ |
#define READ_VALUE { cpu->memory_rw(cpu, cpu->mem, cpu->cd.x86.tr_base + \ |
621 |
int segment = 1, rpl, orig_selector = selector; |
int segment = 1, rpl, orig_selector = selector; |
622 |
unsigned char descr[8]; |
unsigned char descr[8]; |
623 |
char *table_name = "GDT"; |
char *table_name = "GDT"; |
624 |
uint64_t base, limit, table_base, table_limit; |
uint64_t base, limit, table_base; |
625 |
|
int64_t table_limit; |
626 |
|
|
627 |
if (segnr > 0x100) /* arbitrary, larger than N_X86_SEGS */ |
if (segnr > 0x100) /* arbitrary, larger than N_X86_SEGS */ |
628 |
segment = 0; |
segment = 0; |
1401 |
* The rest of running tells us the default (code) operand size. |
* The rest of running tells us the default (code) operand size. |
1402 |
*/ |
*/ |
1403 |
int x86_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int x86_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
1404 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
1405 |
{ |
{ |
1406 |
int op, rep = 0, lock = 0, n_prefix_bytes = 0; |
int op, rep = 0, lock = 0, n_prefix_bytes = 0; |
1407 |
uint64_t ilen = 0, offset; |
uint64_t ilen = 0, offset; |
2337 |
* |
* |
2338 |
* TODO: Level 1 and 2 info. |
* TODO: Level 1 and 2 info. |
2339 |
*/ |
*/ |
2340 |
static void x86_cpuid(struct cpu *cpu) |
void x86_cpuid(struct cpu *cpu) |
2341 |
{ |
{ |
2342 |
switch (cpu->cd.x86.r[X86_R_AX]) { |
switch (cpu->cd.x86.r[X86_R_AX]) { |
2343 |
/* Normal CPU id: */ |
/* Normal CPU id: */ |
2505 |
if (PROTECTED_MODE) { |
if (PROTECTED_MODE) { |
2506 |
int i, int_type = 0; |
int i, int_type = 0; |
2507 |
|
|
2508 |
if (nr * 8 > cpu->cd.x86.idtr_limit) { |
if (nr * 8 > (int)cpu->cd.x86.idtr_limit) { |
2509 |
fatal("TODO: protected mode int 0x%02x outside idtr" |
fatal("TODO: protected mode int 0x%02x outside idtr" |
2510 |
" limit (%i)?\n", nr, (int)cpu->cd.x86.idtr_limit); |
" limit (%i)?\n", nr, (int)cpu->cd.x86.idtr_limit); |
2511 |
cpu->running = 0; |
cpu->running = 0; |
2647 |
/* |
/* |
2648 |
* Real mode: |
* Real mode: |
2649 |
*/ |
*/ |
2650 |
if (nr * 4 > cpu->cd.x86.idtr_limit) { |
if (nr * 4 > (int)cpu->cd.x86.idtr_limit) { |
2651 |
fatal("TODO: real mode int 0x%02x outside idtr limit (" |
fatal("TODO: real mode int 0x%02x outside idtr limit (" |
2652 |
"%i)?\n", nr, (int)cpu->cd.x86.idtr_limit); |
"%i)?\n", nr, (int)cpu->cd.x86.idtr_limit); |
2653 |
cpu->running = 0; |
cpu->running = 0; |
3034 |
} |
} |
3035 |
|
|
3036 |
|
|
3037 |
#define TRANSLATE_ADDRESS x86_translate_address |
#define TRANSLATE_ADDRESS x86_translate_v2p |
3038 |
#include "memory_x86.c" |
#include "memory_x86.c" |
3039 |
#undef TRANSLATE_ADDRESS |
#undef TRANSLATE_ADDRESS |
3040 |
|
|