/[gxemul]/trunk/src/cpus/cpu_transputer_instr.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/cpu_transputer_instr.c

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 5653 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 /*
2 * Copyright (C) 2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_transputer_instr.c,v 1.2 2006/07/21 05:46:45 debug Exp $
29 *
30 * INMOS transputer instructions.
31 *
32 * Individual functions should keep track of cpu->n_translated_instrs.
33 * (n_translated_instrs is automatically increased by 1 for each function
34 * call. If no instruction was executed, then it should be decreased. If, say,
35 * 4 instructions were combined into one function and executed, then it should
36 * be increased by 3.)
37 */
38
39
40 /*
41 * nop: Do nothing.
42 */
43 X(nop)
44 {
45 }
46
47
48 /*****************************************************************************/
49
50
51 /*
52 * j: Relative jump
53 *
54 * arg[0] = relative distance from the _current_ instruction.
55 */
56 X(j)
57 {
58 /* Synchronize the PC and then add the operand + 1: */
59 int low_pc = ((size_t)ic - (size_t)cpu->cd.transputer.cur_ic_page)
60 / sizeof(struct transputer_instr_call);
61 cpu->pc &= ~(TRANSPUTER_IC_ENTRIES_PER_PAGE-1);
62 cpu->pc += low_pc + ic->arg[0];
63 quick_pc_to_pointers(cpu);
64 }
65
66
67 /*
68 * ldc: Load constant
69 *
70 * arg[0] = constant
71 */
72 X(ldc)
73 {
74 /* TODO: Is oreg really cleared like this? */
75 cpu->cd.transputer.oreg = ic->arg[0];
76 cpu->cd.transputer.c = cpu->cd.transputer.b;
77 cpu->cd.transputer.b = cpu->cd.transputer.a;
78 cpu->cd.transputer.a = ic->arg[0];
79 }
80
81
82 /*****************************************************************************/
83
84
85 X(end_of_page)
86 {
87 /* Update the PC: (offset 0, but on the next page) */
88 cpu->pc &= ~((TRANSPUTER_IC_ENTRIES_PER_PAGE-1) << 1);
89 cpu->pc += (TRANSPUTER_IC_ENTRIES_PER_PAGE << 1);
90
91 /* Find the new physical page and update the translation pointers: */
92 transputer_pc_to_pointers(cpu);
93
94 /* end_of_page doesn't count as an executed instruction: */
95 cpu->n_translated_instrs --;
96 }
97
98
99 /*****************************************************************************/
100
101
102 /*
103 * transputer_instr_to_be_translated():
104 *
105 * Translate an instruction word into an transputer_instr_call. ic is filled in with
106 * valid data for the translated instruction, or a "nothing" instruction if
107 * there was a translation failure. The newly translated instruction is then
108 * executed.
109 */
110 X(to_be_translated)
111 {
112 uint32_t addr, low_pc;
113 unsigned char *page;
114 unsigned char ib[1];
115 /* void (*samepage_function)(struct cpu *,
116 struct transputer_instr_call *);*/
117
118 /* Figure out the (virtual) address of the instruction: */
119 low_pc = ((size_t)ic - (size_t)cpu->cd.transputer.cur_ic_page)
120 / sizeof(struct transputer_instr_call);
121 addr = cpu->pc & ~((TRANSPUTER_IC_ENTRIES_PER_PAGE-1) <<
122 TRANSPUTER_INSTR_ALIGNMENT_SHIFT);
123 addr += (low_pc << TRANSPUTER_INSTR_ALIGNMENT_SHIFT);
124 cpu->pc = addr;
125 addr &= ~((1 << TRANSPUTER_INSTR_ALIGNMENT_SHIFT) - 1);
126
127 /* Read the instruction word from memory: */
128 page = cpu->cd.transputer.host_load[addr >> 12];
129
130 if (page != NULL) {
131 /* fatal("TRANSLATION HIT!\n"); */
132 memcpy(ib, page + (addr & 0xfff), sizeof(ib));
133 } else {
134 /* fatal("TRANSLATION MISS!\n"); */
135 if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
136 sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
137 fatal("to_be_translated(): "
138 "read failed: TODO\n");
139 goto bad;
140 }
141 }
142
143
144 #define DYNTRANS_TO_BE_TRANSLATED_HEAD
145 #include "cpu_dyntrans.c"
146 #undef DYNTRANS_TO_BE_TRANSLATED_HEAD
147
148
149 /*
150 * Translate the instruction:
151 * --------------------------
152 *
153 * Most instructions take the operand as arg[0], so we set it
154 * here by default:
155 */
156 ic->arg[0] = ib[0] & 0xf;
157
158 switch (ib[0] >> 4) {
159
160 case 0: /* j, relative jump */
161 ic->f = instr(j);
162 ic->arg[0] = (ib[0] & 0xf) + 1;
163 /* TODO: Samepage jump! */
164
165 if (cpu->cd.transputer.cpu_type.features & T_DEBUG
166 && (ib[0] & 0xf) == 0) {
167 /*
168 * From Wikipedia: ... "and, later, the T225. This
169 * added debugging breakpoint support (by extending
170 * the instruction J 0)"
171 */
172 fatal("TODO: Transputer Debugger support!\n");
173 goto bad;
174 }
175 break;
176
177 case 4: /* ldc, load constant */
178 ic->f = instr(ldc);
179 break;
180
181 default:fatal("UNIMPLEMENTED opcode 0x%02x\n", ib[0]);
182 goto bad;
183 }
184
185
186 #define DYNTRANS_TO_BE_TRANSLATED_TAIL
187 #include "cpu_dyntrans.c"
188 #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
189 }
190

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