/[gxemul]/trunk/src/cpus/cpu_transputer.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/cpus/cpu_transputer.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8568 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 /*
2 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_transputer.c,v 1.6 2006/12/30 13:30:55 debug Exp $
29 *
30 * INMOS transputer CPU emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "cpu.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42 #include "settings.h"
43 #include "symbol.h"
44
45 #define DYNTRANS_32
46 #include "tmp_transputer_head.c"
47
48
49 static char *opcode_names[16] = TRANSPUTER_INSTRUCTIONS;
50 static char *opcode_f_names[N_TRANSPUTER_OPC_F_NAMES] = TRANSPUTER_OPC_F_NAMES;
51
52 /*
53 * transputer_cpu_new():
54 *
55 * Create a new TRANSPUTER cpu object.
56 *
57 * Returns 1 on success, 0 if there was no matching TRANSPUTER processor with
58 * this cpu_type_name.
59 */
60 int transputer_cpu_new(struct cpu *cpu, struct memory *mem,
61 struct machine *machine, int cpu_id, char *cpu_type_name)
62 {
63 int i = 0;
64 struct transputer_cpu_type_def cpu_type_defs[] =
65 TRANSPUTER_CPU_TYPE_DEFS;
66
67 /* Scan the cpu_type_defs list for this cpu type: */
68 while (cpu_type_defs[i].name != NULL) {
69 if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
70 break;
71 }
72 i++;
73 }
74 if (cpu_type_defs[i].name == NULL)
75 return 0;
76
77 cpu->cd.transputer.cpu_type = cpu_type_defs[i];
78 cpu->name = cpu->cd.transputer.cpu_type.name;
79 cpu->byte_order = EMUL_LITTLE_ENDIAN;
80 cpu->is_32bit = 1;
81
82 if (cpu->cd.transputer.cpu_type.bits != 32) {
83 fatal("Only 32-bit Transputer processors can be "
84 "emulated. 16-bit mode is not supported. Sorry.\n");
85 exit(1);
86 }
87
88 cpu->run_instr = transputer_run_instr;
89 cpu->memory_rw = transputer_memory_rw;
90 cpu->update_translation_table = transputer_update_translation_table;
91 cpu->invalidate_translation_caches =
92 transputer_invalidate_translation_caches;
93 cpu->invalidate_code_translation =
94 transputer_invalidate_code_translation;
95
96 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
97 if (cpu_id == 0) {
98 debug("%s", cpu->name);
99 }
100
101 cpu->cd.transputer.wptr = machine->physical_ram_in_mb * 1048576 - 2048;
102
103 CPU_SETTINGS_ADD_REGISTER64("ip", cpu->pc);
104 CPU_SETTINGS_ADD_REGISTER32("a", cpu->cd.transputer.a);
105 CPU_SETTINGS_ADD_REGISTER32("b", cpu->cd.transputer.b);
106 CPU_SETTINGS_ADD_REGISTER32("c", cpu->cd.transputer.c);
107 CPU_SETTINGS_ADD_REGISTER32("oreg", cpu->cd.transputer.oreg);
108 CPU_SETTINGS_ADD_REGISTER32("wptr", cpu->cd.transputer.wptr);
109
110 return 1;
111 }
112
113
114 /*
115 * transputer_cpu_list_available_types():
116 *
117 * Print a list of available TRANSPUTER CPU types.
118 */
119 void transputer_cpu_list_available_types(void)
120 {
121 int i = 0, j;
122 struct transputer_cpu_type_def tdefs[] = TRANSPUTER_CPU_TYPE_DEFS;
123
124 while (tdefs[i].name != NULL) {
125 debug("%s", tdefs[i].name);
126 for (j = 7 - strlen(tdefs[i].name); j > 0; j --)
127 debug(" ");
128 i ++;
129 if ((i % 8) == 0 || tdefs[i].name == NULL)
130 debug("\n");
131 }
132 }
133
134
135 /*
136 * transputer_cpu_dumpinfo():
137 */
138 void transputer_cpu_dumpinfo(struct cpu *cpu)
139 {
140 /* TODO */
141 debug("\n");
142 }
143
144
145 /*
146 * transputer_cpu_register_dump():
147 *
148 * Dump cpu registers in a relatively readable format.
149 *
150 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
151 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
152 */
153 void transputer_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
154 {
155 char *symbol;
156 uint64_t offset;
157 int x = cpu->cpu_id;
158
159 symbol = get_symbol_name(&cpu->machine->symbol_context,
160 cpu->pc, &offset);
161
162 debug("cpu%i: wptr = 0x%08"PRIx32" oreg = 0x%08"PRIx32" ip = 0x%08"
163 PRIx32, x, cpu->cd.transputer.wptr, cpu->cd.transputer.oreg,
164 (uint32_t)cpu->pc);
165 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
166
167 debug("cpu%i: a = 0x%08"PRIx32" b = 0x%08"PRIx32" c = 0x%08"
168 PRIx32"\n", x, cpu->cd.transputer.a, cpu->cd.transputer.b,
169 cpu->cd.transputer.c);
170
171 /* TODO: Error flags, Floating point registers, etc. */
172 }
173
174
175 /*
176 * transputer_cpu_tlbdump():
177 *
178 * Called from the debugger to dump the TLB in a readable format.
179 * x is the cpu number to dump, or -1 to dump all CPUs.
180 *
181 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
182 * just dumped.
183 */
184 void transputer_cpu_tlbdump(struct machine *m, int x, int rawflag)
185 {
186 }
187
188
189 /*
190 * transputer_cpu_gdb_stub():
191 *
192 * Execute a "remote GDB" command. Returns a newly allocated response string
193 * on success, NULL on failure.
194 */
195 char *transputer_cpu_gdb_stub(struct cpu *cpu, char *cmd)
196 {
197 fatal("transputer_cpu_gdb_stub(): TODO\n");
198 return NULL;
199 }
200
201
202 /*
203 * transputer_cpu_interrupt():
204 */
205 int transputer_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
206 {
207 fatal("transputer_cpu_interrupt(): TODO\n");
208 return 0;
209 }
210
211
212 /*
213 * transputer_cpu_interrupt_ack():
214 */
215 int transputer_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
216 {
217 /* fatal("transputer_cpu_interrupt_ack(): TODO\n"); */
218 return 0;
219 }
220
221
222 /*
223 * transputer_cpu_disassemble_instr():
224 *
225 * Convert an instruction word into human readable format, for instruction
226 * tracing. On Transputers, an opcode is one byte, optionally followed by
227 * more instruction bytes.
228 *
229 * If running is 1, cpu->pc should be the address of the instruction.
230 *
231 * If running is 0, things that depend on the runtime environment (eg.
232 * register contents) will not be shown, and addr will be used instead of
233 * cpu->pc for relative addresses.
234 */
235 int transputer_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
236 int running, uint64_t dumpaddr)
237 {
238 uint64_t offset;
239 char *symbol;
240 int opcode, operand;
241
242 if (running)
243 dumpaddr = cpu->pc;
244
245 symbol = get_symbol_name(&cpu->machine->symbol_context,
246 dumpaddr, &offset);
247 if (symbol != NULL && offset==0)
248 debug("<%s>\n", symbol);
249
250 if (cpu->machine->ncpus > 1 && running)
251 debug("cpu%i: ", cpu->cpu_id);
252
253 debug("0x%08x: ", (int)dumpaddr);
254
255 opcode = ib[0] >> 4;
256 operand = ib[0] & 15;
257 debug("%02x %-6s %2i", ib[0], opcode_names[opcode], operand);
258
259 /*
260 * For opcodes where it is nice to have additional runtime info,
261 * special cases need to be added here. (E.g. an instruction which
262 * updates registers can show the contents of the new registers
263 * after the update.)
264 */
265
266 switch (opcode) {
267
268 case T_OPC_PFIX:
269 if (running) {
270 uint32_t oreg = cpu->cd.transputer.oreg | operand;
271 debug("\toreg = 0x%"PRIx32, oreg << 4);
272 }
273 break;
274
275 case T_OPC_LDC:
276 if (running) {
277 uint32_t new_c = cpu->cd.transputer.b;
278 uint32_t new_b = cpu->cd.transputer.a;
279 uint32_t new_a = cpu->cd.transputer.oreg | operand;
280 debug("\ta=0x%"PRIx32", b=0x%"PRIx32", c=0x%"PRIx32,
281 new_a, new_b, new_c);
282 }
283 break;
284
285 case T_OPC_STL:
286 if (running) {
287 uint32_t addr = (cpu->cd.transputer.oreg | operand)
288 * sizeof(uint32_t) + cpu->cd.transputer.wptr;
289 debug("\t[0x%"PRIx32"] = 0x%x", addr,
290 cpu->cd.transputer.a);
291 }
292 break;
293
294 case T_OPC_OPR:
295 if (running) {
296 uint32_t fopcode = cpu->cd.transputer.oreg | operand;
297 debug("\t");
298 if (fopcode < N_TRANSPUTER_OPC_F_NAMES)
299 debug("%s", opcode_f_names[fopcode]);
300 else
301 debug("0x%"PRIx32, fopcode);
302 }
303 break;
304
305 }
306
307 debug("\n");
308
309 return 1;
310 }
311
312
313 #include "tmp_transputer_tail.c"
314

  ViewVC Help
Powered by ViewVC 1.1.26