/[gxemul]/trunk/src/cpus/cpu_transputer.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Annotation of /trunk/src/cpus/cpu_transputer.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 7381 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 dpavlin 28 /*
2     * Copyright (C) 2006 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28     * $Id: cpu_transputer.c,v 1.1 2006/07/20 21:52:59 debug Exp $
29     *
30     * INMOS transputer CPU emulation.
31     */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36     #include <ctype.h>
37    
38     #include "cpu.h"
39     #include "machine.h"
40     #include "memory.h"
41     #include "misc.h"
42     #include "symbol.h"
43    
44     #define DYNTRANS_32
45     #include "tmp_transputer_head.c"
46    
47    
48     static char *opcode_names[16] = TRANSPUTER_INSTRUCTIONS;
49    
50    
51     /*
52     * transputer_cpu_new():
53     *
54     * Create a new TRANSPUTER cpu object.
55     *
56     * Returns 1 on success, 0 if there was no matching TRANSPUTER processor with
57     * this cpu_type_name.
58     */
59     int transputer_cpu_new(struct cpu *cpu, struct memory *mem,
60     struct machine *machine, int cpu_id, char *cpu_type_name)
61     {
62     int i = 0;
63     struct transputer_cpu_type_def cpu_type_defs[] =
64     TRANSPUTER_CPU_TYPE_DEFS;
65    
66     /* Scan the cpu_type_defs list for this cpu type: */
67     while (cpu_type_defs[i].name != NULL) {
68     if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
69     break;
70     }
71     i++;
72     }
73     if (cpu_type_defs[i].name == NULL)
74     return 0;
75    
76     cpu->cd.transputer.cpu_type = cpu_type_defs[i];
77     cpu->name = cpu->cd.transputer.cpu_type.name;
78     cpu->byte_order = EMUL_LITTLE_ENDIAN;
79     cpu->is_32bit = 1;
80    
81     if (cpu->cd.transputer.cpu_type.bits != 32) {
82     fatal("Only 32-bit Transputer processors can be "
83     "emulated. 16-bit mode is not supported. Sorry.\n");
84     exit(1);
85     }
86    
87     cpu->run_instr = transputer_run_instr;
88     cpu->memory_rw = transputer_memory_rw;
89     cpu->update_translation_table = transputer_update_translation_table;
90     cpu->invalidate_translation_caches =
91     transputer_invalidate_translation_caches;
92     cpu->invalidate_code_translation =
93     transputer_invalidate_code_translation;
94    
95     /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
96     if (cpu_id == 0) {
97     debug("%s", cpu->name);
98     }
99    
100     return 1;
101     }
102    
103    
104     /*
105     * transputer_cpu_list_available_types():
106     *
107     * Print a list of available TRANSPUTER CPU types.
108     */
109     void transputer_cpu_list_available_types(void)
110     {
111     int i = 0, j;
112     struct transputer_cpu_type_def tdefs[] = TRANSPUTER_CPU_TYPE_DEFS;
113    
114     while (tdefs[i].name != NULL) {
115     debug("%s", tdefs[i].name);
116     for (j = 7 - strlen(tdefs[i].name); j > 0; j --)
117     debug(" ");
118     i ++;
119     if ((i % 8) == 0 || tdefs[i].name == NULL)
120     debug("\n");
121     }
122     }
123    
124    
125     /*
126     * transputer_cpu_dumpinfo():
127     */
128     void transputer_cpu_dumpinfo(struct cpu *cpu)
129     {
130     /* TODO */
131     debug("\n");
132     }
133    
134    
135     /*
136     * transputer_cpu_register_dump():
137     *
138     * Dump cpu registers in a relatively readable format.
139     *
140     * gprs: set to non-zero to dump GPRs and some special-purpose registers.
141     * coprocs: set bit 0..3 to dump registers in coproc 0..3.
142     */
143     void transputer_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
144     {
145     char *symbol;
146     uint64_t offset;
147     int x = cpu->cpu_id;
148    
149     symbol = get_symbol_name(&cpu->machine->symbol_context,
150     cpu->pc, &offset);
151    
152     debug("cpu%i: wptr = 0x%08"PRIx32" oreg = 0x%08"PRIx32" ip = 0x%08"
153     PRIx32, x, cpu->cd.transputer.wptr, cpu->cd.transputer.oreg,
154     (uint32_t)cpu->pc);
155     debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
156    
157     debug("cpu%i: a = 0x%08"PRIx32" b = 0x%08"PRIx32" c = 0x%08"
158     PRIx32"\n", x, cpu->cd.transputer.a, cpu->cd.transputer.b,
159     cpu->cd.transputer.c);
160    
161     /* TODO: Error flags, Floating point registers, etc. */
162     }
163    
164    
165     /*
166     * transputer_cpu_register_match():
167     */
168     void transputer_cpu_register_match(struct machine *m, char *name,
169     int writeflag, uint64_t *valuep, int *match_register)
170     {
171     int cpunr = 0;
172    
173     /* CPU number: */
174     /* TODO */
175    
176     /* Register name: */
177     if (strcasecmp(name, "pc") == 0) {
178     if (writeflag) {
179     m->cpus[cpunr]->pc = *valuep;
180     } else
181     *valuep = m->cpus[cpunr]->pc;
182     *match_register = 1;
183     }
184    
185     /* TODO */
186     /* More register names... */
187     }
188    
189    
190     /*
191     * transputer_cpu_tlbdump():
192     *
193     * Called from the debugger to dump the TLB in a readable format.
194     * x is the cpu number to dump, or -1 to dump all CPUs.
195     *
196     * If rawflag is nonzero, then the TLB contents isn't formated nicely,
197     * just dumped.
198     */
199     void transputer_cpu_tlbdump(struct machine *m, int x, int rawflag)
200     {
201     }
202    
203    
204     /*
205     * transputer_cpu_gdb_stub():
206     *
207     * Execute a "remote GDB" command. Returns a newly allocated response string
208     * on success, NULL on failure.
209     */
210     char *transputer_cpu_gdb_stub(struct cpu *cpu, char *cmd)
211     {
212     fatal("transputer_cpu_gdb_stub(): TODO\n");
213     return NULL;
214     }
215    
216    
217     /*
218     * transputer_cpu_interrupt():
219     */
220     int transputer_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
221     {
222     fatal("transputer_cpu_interrupt(): TODO\n");
223     return 0;
224     }
225    
226    
227     /*
228     * transputer_cpu_interrupt_ack():
229     */
230     int transputer_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
231     {
232     /* fatal("transputer_cpu_interrupt_ack(): TODO\n"); */
233     return 0;
234     }
235    
236    
237     /*
238     * transputer_cpu_disassemble_instr():
239     *
240     * Convert an instruction word into human readable format, for instruction
241     * tracing. On Transputers, an opcode is one byte, optionally followed by
242     * more instruction bytes.
243     *
244     * If running is 1, cpu->pc should be the address of the instruction.
245     *
246     * If running is 0, things that depend on the runtime environment (eg.
247     * register contents) will not be shown, and addr will be used instead of
248     * cpu->pc for relative addresses.
249     */
250     int transputer_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
251     int running, uint64_t dumpaddr)
252     {
253     uint64_t offset;
254     char *symbol;
255     int opcode, operand;
256    
257     if (running)
258     dumpaddr = cpu->pc;
259    
260     symbol = get_symbol_name(&cpu->machine->symbol_context,
261     dumpaddr, &offset);
262     if (symbol != NULL && offset==0)
263     debug("<%s>\n", symbol);
264    
265     if (cpu->machine->ncpus > 1 && running)
266     debug("cpu%i: ", cpu->cpu_id);
267    
268     debug("0x%08x: ", (int)dumpaddr);
269    
270     opcode = ib[0] >> 4;
271     operand = ib[0] & 15;
272    
273     debug("%02x ", ib[0]);
274    
275     switch (opcode >> 4) {
276    
277     default:debug("%-6s %2i\n", opcode_names[opcode], operand);
278     }
279    
280     return 1;
281     }
282    
283    
284     #include "tmp_transputer_tail.c"
285    

  ViewVC Help
Powered by ViewVC 1.1.26