/[gxemul]/trunk/src/cpus/cpu_sparc_instr_loadstore.c
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Contents of /trunk/src/cpus/cpu_sparc_instr_loadstore.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 6371 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 /*
2 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_sparc_instr_loadstore.c,v 1.4 2006/12/30 13:30:55 debug Exp $
29 *
30 * SPARC load/store instructions; the following args are used:
31 *
32 * arg[0] = pointer to the register to load to or store from
33 * arg[1] = pointer to the base register
34 * arg[2] = if LS_USE_IMM is defined: an int32_t immediate offset
35 * otherwise: pointer to the offset register
36 */
37
38
39 void LS_GENERIC_N(struct cpu *cpu, struct sparc_instr_call *ic)
40 {
41 MODE_int_t addr = reg(ic->arg[1]) +
42 #ifdef LS_USE_IMM
43 (int32_t)ic->arg[2];
44 #else
45 reg(ic->arg[2]);
46 #endif
47 uint8_t data[LS_SIZE];
48 #ifdef LS_LOAD
49 uint64_t x;
50 #endif
51
52 /* Synchronize the PC: */
53 int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page)
54 / sizeof(struct sparc_instr_call);
55 cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1)
56 << SPARC_INSTR_ALIGNMENT_SHIFT);
57 cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT);
58
59 #ifndef LS_1
60 /* Check alignment: */
61 if (addr & (LS_SIZE - 1)) {
62 fatal("TODO: sparc dyntrans alignment exception, size = %i,"
63 " addr = %016"PRIx64", pc = %016"PRIx64"\n", LS_SIZE,
64 (uint64_t) addr, cpu->pc);
65
66 /* TODO: Generalize this into a abort_call, or similar: */
67 cpu->running = 0;
68 debugger_n_steps_left_before_interaction = 0;
69 cpu->cd.sparc.next_ic = &nothing_call;
70 return;
71 }
72 #endif
73
74 #ifdef LS_LOAD
75 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
76 MEM_READ, CACHE_DATA)) {
77 /* Exception. */
78 return;
79 }
80 x = memory_readmax64(cpu, data, LS_SIZE);
81 #ifdef LS_SIGNED
82 #ifdef LS_1
83 x = (int8_t)x;
84 #endif
85 #ifdef LS_2
86 x = (int16_t)x;
87 #endif
88 #ifdef LS_4
89 x = (int32_t)x;
90 #endif
91 #endif
92 reg(ic->arg[0]) = x;
93 #else /* LS_STORE: */
94 memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0]));
95 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
96 MEM_WRITE, CACHE_DATA)) {
97 /* Exception. */
98 return;
99 }
100 #endif
101 }
102
103
104 void LS_N(struct cpu *cpu, struct sparc_instr_call *ic)
105 {
106 MODE_uint_t addr = reg(ic->arg[1]) +
107 #ifdef LS_USE_IMM
108 (int32_t)ic->arg[2];
109 #else
110 reg(ic->arg[2]);
111 #endif
112 unsigned char *p;
113 #ifdef MODE32
114 #ifdef LS_LOAD
115 p = cpu->cd.sparc.host_load[addr >> 12];
116 #else
117 p = cpu->cd.sparc.host_store[addr >> 12];
118 #endif
119 #else /* !MODE32 */
120 const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
121 const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
122 const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
123 uint32_t x1, x2, x3;
124 struct DYNTRANS_L2_64_TABLE *l2;
125 struct DYNTRANS_L3_64_TABLE *l3;
126
127 x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
128 x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
129 x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
130 /* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
131 (uint64_t) addr, (int) x1, (int) x2, (int) x3); */
132 l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
133 /* fatal(" l2 = %p\n", l2); */
134 l3 = l2->l3[x2];
135 /* fatal(" l3 = %p\n", l3); */
136 #ifdef LS_LOAD
137 p = l3->host_load[x3];
138 #else
139 p = l3->host_store[x3];
140 #endif
141 /* fatal(" p = %p\n", p); */
142 #endif
143
144 if (p == NULL
145 #ifndef LS_1
146 || addr & (LS_SIZE - 1)
147 #endif
148 ) {
149 LS_GENERIC_N(cpu, ic);
150 return;
151 }
152
153 addr &= 0xfff;
154
155 #ifdef LS_LOAD
156 /* Load: */
157
158 #ifdef LS_1
159 reg(ic->arg[0]) =
160 #ifdef LS_SIGNED
161 (int8_t)
162 #endif
163 p[addr];
164 #endif /* LS_1 */
165
166 #ifdef LS_2
167 reg(ic->arg[0]) =
168 #ifdef LS_SIGNED
169 (int16_t)
170 #endif
171 #ifdef HOST_BIG_ENDIAN
172 ( *(uint16_t *)(p + addr) );
173 #else
174 ((p[addr]<<8) + p[addr+1]);
175 #endif
176 #endif /* LS_2 */
177
178 #ifdef LS_4
179 reg(ic->arg[0]) =
180 #ifdef LS_SIGNED
181 (int32_t)
182 #else
183 (uint32_t)
184 #endif
185 #ifdef HOST_BIG_ENDIAN
186 ( *(uint32_t *)(p + addr) );
187 #else
188 ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
189 #endif
190 #endif /* LS_4 */
191
192 #ifdef LS_8
193 *((uint64_t *)ic->arg[0]) =
194 #ifdef HOST_BIG_ENDIAN
195 ( *(uint64_t *)(p + addr) );
196 #else
197 ((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) +
198 ((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) +
199 ((uint64_t)p[addr+4] << 24) +
200 (p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7];
201 #endif
202 #endif /* LS_8 */
203
204 #else
205 /* Store: */
206
207 #ifdef LS_1
208 p[addr] = reg(ic->arg[0]);
209 #endif
210 #ifdef LS_2
211 { uint32_t x = reg(ic->arg[0]);
212 #ifdef HOST_BIG_ENDIAN
213 *((uint16_t *)(p+addr)) = x; }
214 #else
215 p[addr] = x >> 8; p[addr+1] = x; }
216 #endif
217 #endif /* LS_2 */
218 #ifdef LS_4
219 { uint32_t x = reg(ic->arg[0]);
220 #ifdef HOST_BIG_ENDIAN
221 *((uint32_t *)(p+addr)) = x; }
222 #else
223 p[addr] = x >> 24; p[addr+1] = x >> 16;
224 p[addr+2] = x >> 8; p[addr+3] = x; }
225 #endif
226 #endif /* LS_4 */
227 #ifdef LS_8
228 { uint64_t x = *(uint64_t *)(ic->arg[0]);
229 #ifdef HOST_BIG_ENDIAN
230 *((uint64_t *)(p+addr)) = x; }
231 #else
232 p[addr] = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40;
233 p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16;
234 p[addr+6] = x >> 8; p[addr+7] = x; }
235 #endif
236 #endif /* LS_8 */
237
238 #endif /* store */
239 }
240

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