/[gxemul]/trunk/src/cpus/cpu_sparc_instr_loadstore.c
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Contents of /trunk/src/cpus/cpu_sparc_instr_loadstore.c

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 6414 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============
1 /*
2 * Copyright (C) 2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_sparc_instr_loadstore.c,v 1.2 2006/07/02 11:10:20 debug Exp $
29 *
30 * SPARC load/store instructions; the following args are used:
31 *
32 * arg[0] = pointer to the register to load to or store from
33 * arg[1] = pointer to the base register
34 * arg[2] = if LS_USE_IMM is defined: an int32_t immediate offset
35 * otherwise: pointer to the offset register
36 */
37
38
39 void LS_GENERIC_N(struct cpu *cpu, struct sparc_instr_call *ic)
40 {
41 MODE_int_t addr = reg(ic->arg[1]) +
42 #ifdef LS_USE_IMM
43 (int32_t)ic->arg[2];
44 #else
45 reg(ic->arg[2]);
46 #endif
47 uint8_t data[LS_SIZE];
48 #ifdef LS_LOAD
49 uint64_t x;
50 #endif
51
52 /* Synchronize the PC: */
53 int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page)
54 / sizeof(struct sparc_instr_call);
55 cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1)
56 << SPARC_INSTR_ALIGNMENT_SHIFT);
57 cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT);
58
59 #ifndef LS_1
60 /* Check alignment: */
61 if (addr & (LS_SIZE - 1)) {
62 fatal("TODO: sparc dyntrans alignment exception, size = %i,"
63 " addr = %016"PRIx64", pc = %016"PRIx64"\n", LS_SIZE,
64 (uint64_t) addr, cpu->pc);
65
66 /* TODO: Generalize this into a abort_call, or similar: */
67 cpu->running = 0;
68 cpu->dead = 1;
69 debugger_n_steps_left_before_interaction = 0;
70 cpu->running_translated = 0;
71 cpu->cd.sparc.next_ic = &nothing_call;
72 return;
73 }
74 #endif
75
76 #ifdef LS_LOAD
77 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
78 MEM_READ, CACHE_DATA)) {
79 /* Exception. */
80 return;
81 }
82 x = memory_readmax64(cpu, data, LS_SIZE);
83 #ifdef LS_SIGNED
84 #ifdef LS_1
85 x = (int8_t)x;
86 #endif
87 #ifdef LS_2
88 x = (int16_t)x;
89 #endif
90 #ifdef LS_4
91 x = (int32_t)x;
92 #endif
93 #endif
94 reg(ic->arg[0]) = x;
95 #else /* LS_STORE: */
96 memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0]));
97 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
98 MEM_WRITE, CACHE_DATA)) {
99 /* Exception. */
100 return;
101 }
102 #endif
103 }
104
105
106 void LS_N(struct cpu *cpu, struct sparc_instr_call *ic)
107 {
108 MODE_uint_t addr = reg(ic->arg[1]) +
109 #ifdef LS_USE_IMM
110 (int32_t)ic->arg[2];
111 #else
112 reg(ic->arg[2]);
113 #endif
114 unsigned char *p;
115 #ifdef MODE32
116 #ifdef LS_LOAD
117 p = cpu->cd.sparc.host_load[addr >> 12];
118 #else
119 p = cpu->cd.sparc.host_store[addr >> 12];
120 #endif
121 #else /* !MODE32 */
122 const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
123 const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
124 const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
125 uint32_t x1, x2, x3;
126 struct DYNTRANS_L2_64_TABLE *l2;
127 struct DYNTRANS_L3_64_TABLE *l3;
128
129 x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
130 x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
131 x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
132 /* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
133 (uint64_t) addr, (int) x1, (int) x2, (int) x3); */
134 l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
135 /* fatal(" l2 = %p\n", l2); */
136 l3 = l2->l3[x2];
137 /* fatal(" l3 = %p\n", l3); */
138 #ifdef LS_LOAD
139 p = l3->host_load[x3];
140 #else
141 p = l3->host_store[x3];
142 #endif
143 /* fatal(" p = %p\n", p); */
144 #endif
145
146 if (p == NULL
147 #ifndef LS_1
148 || addr & (LS_SIZE - 1)
149 #endif
150 ) {
151 LS_GENERIC_N(cpu, ic);
152 return;
153 }
154
155 addr &= 0xfff;
156
157 #ifdef LS_LOAD
158 /* Load: */
159
160 #ifdef LS_1
161 reg(ic->arg[0]) =
162 #ifdef LS_SIGNED
163 (int8_t)
164 #endif
165 p[addr];
166 #endif /* LS_1 */
167
168 #ifdef LS_2
169 reg(ic->arg[0]) =
170 #ifdef LS_SIGNED
171 (int16_t)
172 #endif
173 #ifdef HOST_BIG_ENDIAN
174 ( *(uint16_t *)(p + addr) );
175 #else
176 ((p[addr]<<8) + p[addr+1]);
177 #endif
178 #endif /* LS_2 */
179
180 #ifdef LS_4
181 reg(ic->arg[0]) =
182 #ifdef LS_SIGNED
183 (int32_t)
184 #else
185 (uint32_t)
186 #endif
187 #ifdef HOST_BIG_ENDIAN
188 ( *(uint32_t *)(p + addr) );
189 #else
190 ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
191 #endif
192 #endif /* LS_4 */
193
194 #ifdef LS_8
195 *((uint64_t *)ic->arg[0]) =
196 #ifdef HOST_BIG_ENDIAN
197 ( *(uint64_t *)(p + addr) );
198 #else
199 ((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) +
200 ((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) +
201 ((uint64_t)p[addr+4] << 24) +
202 (p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7];
203 #endif
204 #endif /* LS_8 */
205
206 #else
207 /* Store: */
208
209 #ifdef LS_1
210 p[addr] = reg(ic->arg[0]);
211 #endif
212 #ifdef LS_2
213 { uint32_t x = reg(ic->arg[0]);
214 #ifdef HOST_BIG_ENDIAN
215 *((uint16_t *)(p+addr)) = x; }
216 #else
217 p[addr] = x >> 8; p[addr+1] = x; }
218 #endif
219 #endif /* LS_2 */
220 #ifdef LS_4
221 { uint32_t x = reg(ic->arg[0]);
222 #ifdef HOST_BIG_ENDIAN
223 *((uint32_t *)(p+addr)) = x; }
224 #else
225 p[addr] = x >> 24; p[addr+1] = x >> 16;
226 p[addr+2] = x >> 8; p[addr+3] = x; }
227 #endif
228 #endif /* LS_4 */
229 #ifdef LS_8
230 { uint64_t x = *(uint64_t *)(ic->arg[0]);
231 #ifdef HOST_BIG_ENDIAN
232 *((uint64_t *)(p+addr)) = x; }
233 #else
234 p[addr] = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40;
235 p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16;
236 p[addr+6] = x >> 8; p[addr+7] = x; }
237 #endif
238 #endif /* LS_8 */
239
240 #endif /* store */
241 }
242
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