1 |
/* |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_sparc_instr.c,v 1.23 2006/07/24 22:32:44 debug Exp $ |
* $Id: cpu_sparc_instr.c,v 1.27 2007/03/16 15:43:58 debug Exp $ |
29 |
* |
* |
30 |
* SPARC instructions. |
* SPARC instructions. |
31 |
* |
* |
155 |
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|
156 |
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|
157 |
/* |
/* |
158 |
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* ble |
159 |
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* |
160 |
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* arg[0] = int32_t displacement compared to the start of the current page |
161 |
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*/ |
162 |
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X(ble) |
163 |
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{ |
164 |
|
MODE_uint_t old_pc = cpu->pc; |
165 |
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int n = (cpu->cd.sparc.ccr & SPARC_CCR_N) ? 1 : 0; |
166 |
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int v = (cpu->cd.sparc.ccr & SPARC_CCR_V) ? 1 : 0; |
167 |
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int z = (cpu->cd.sparc.ccr & SPARC_CCR_Z) ? 1 : 0; |
168 |
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int cond = (n ^ v) || z; |
169 |
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cpu->delay_slot = TO_BE_DELAYED; |
170 |
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ic[1].f(cpu, ic+1); |
171 |
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cpu->n_translated_instrs ++; |
172 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
173 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
174 |
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cpu->delay_slot = NOT_DELAYED; |
175 |
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if (cond) { |
176 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
177 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
178 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
179 |
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quick_pc_to_pointers(cpu); |
180 |
|
} |
181 |
|
} else |
182 |
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cpu->delay_slot = NOT_DELAYED; |
183 |
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} |
184 |
|
X(ble_xcc) |
185 |
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{ |
186 |
|
MODE_uint_t old_pc = cpu->pc; |
187 |
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int n = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_N)? 1:0; |
188 |
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int v = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_V)? 1:0; |
189 |
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int z = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_Z)? 1:0; |
190 |
|
int cond = (n ^ v) || z; |
191 |
|
cpu->delay_slot = TO_BE_DELAYED; |
192 |
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ic[1].f(cpu, ic+1); |
193 |
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cpu->n_translated_instrs ++; |
194 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
195 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
196 |
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cpu->delay_slot = NOT_DELAYED; |
197 |
|
if (cond) { |
198 |
|
old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
199 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
200 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
201 |
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quick_pc_to_pointers(cpu); |
202 |
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} |
203 |
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} else |
204 |
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cpu->delay_slot = NOT_DELAYED; |
205 |
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} |
206 |
|
|
207 |
|
|
208 |
|
/* |
209 |
* bne |
* bne |
210 |
* |
* |
211 |
* arg[0] = int32_t displacement compared to the start of the current page |
* arg[0] = int32_t displacement compared to the start of the current page |
449 |
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|
450 |
|
|
451 |
/* |
/* |
452 |
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* Save: |
453 |
|
* |
454 |
|
* arg[0] = ptr to rs1 |
455 |
|
* arg[1] = ptr to rs2 or an immediate value (int32_t) |
456 |
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* arg[2] = ptr to rd (_after_ the register window change) |
457 |
|
*/ |
458 |
|
X(save_v9_imm) |
459 |
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{ |
460 |
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MODE_uint_t rs = reg(ic->arg[0]) + (int32_t)ic->arg[1]; |
461 |
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int cwp = cpu->cd.sparc.cwp; |
462 |
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|
463 |
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if (cpu->cd.sparc.cansave == 0) { |
464 |
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fatal("save_v9_imm: spill trap. TODO\n"); |
465 |
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exit(1); |
466 |
|
} |
467 |
|
|
468 |
|
if (cpu->cd.sparc.cleanwin - cpu->cd.sparc.canrestore == 0) { |
469 |
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fatal("save_v9_imm: clean_window trap. TODO\n"); |
470 |
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exit(1); |
471 |
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} |
472 |
|
|
473 |
|
/* Save away old in registers: */ |
474 |
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memcpy(&cpu->cd.sparc.r_inout[cwp][0], &cpu->cd.sparc.r[SPARC_REG_I0], |
475 |
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sizeof(cpu->cd.sparc.r[SPARC_REG_I0]) * N_SPARC_INOUT_REG); |
476 |
|
|
477 |
|
/* Save away old local registers: */ |
478 |
|
memcpy(&cpu->cd.sparc.r_local[cwp][0], &cpu->cd.sparc.r[SPARC_REG_L0], |
479 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_L0]) * N_SPARC_INOUT_REG); |
480 |
|
|
481 |
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cpu->cd.sparc.cwp = (cwp + 1) % cpu->cd.sparc.cpu_type.nwindows; |
482 |
|
cpu->cd.sparc.cansave --; |
483 |
|
cpu->cd.sparc.canrestore ++; /* TODO: modulo here too? */ |
484 |
|
cwp = cpu->cd.sparc.cwp; |
485 |
|
|
486 |
|
/* The out registers become the new in registers: */ |
487 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_I0], &cpu->cd.sparc.r[SPARC_REG_O0], |
488 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_O0]) * N_SPARC_INOUT_REG); |
489 |
|
|
490 |
|
/* Read new local registers: */ |
491 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_L0], &cpu->cd.sparc.r_local[cwp][0], |
492 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_L0]) * N_SPARC_INOUT_REG); |
493 |
|
|
494 |
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reg(ic->arg[2]) = rs; |
495 |
|
} |
496 |
|
|
497 |
|
|
498 |
|
/* |
499 |
|
* Restore: |
500 |
|
*/ |
501 |
|
X(restore) |
502 |
|
{ |
503 |
|
int cwp = cpu->cd.sparc.cwp; |
504 |
|
|
505 |
|
if (cpu->cd.sparc.canrestore == 0) { |
506 |
|
fatal("restore: spill trap. TODO\n"); |
507 |
|
exit(1); |
508 |
|
} |
509 |
|
|
510 |
|
cpu->cd.sparc.cwp = cwp - 1; |
511 |
|
if (cwp == 0) |
512 |
|
cpu->cd.sparc.cwp = cpu->cd.sparc.cpu_type.nwindows - 1; |
513 |
|
cpu->cd.sparc.cansave ++; |
514 |
|
cpu->cd.sparc.canrestore --; |
515 |
|
cwp = cpu->cd.sparc.cwp; |
516 |
|
|
517 |
|
/* The in registers become the new out registers: */ |
518 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_O0], &cpu->cd.sparc.r[SPARC_REG_I0], |
519 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_O0]) * N_SPARC_INOUT_REG); |
520 |
|
|
521 |
|
/* Read back the local registers: */ |
522 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_L0], &cpu->cd.sparc.r_local[cwp][0], |
523 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_L0]) * N_SPARC_INOUT_REG); |
524 |
|
|
525 |
|
/* Read back the in registers: */ |
526 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_I0], &cpu->cd.sparc.r_inout[cwp][0], |
527 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_I0]) * N_SPARC_INOUT_REG); |
528 |
|
} |
529 |
|
|
530 |
|
|
531 |
|
/* |
532 |
* Jump and link |
* Jump and link |
533 |
* |
* |
534 |
* arg[0] = ptr to rs1 |
* arg[0] = ptr to rs1 |
687 |
|
|
688 |
|
|
689 |
/* |
/* |
690 |
|
* Return |
691 |
|
* |
692 |
|
* arg[0] = ptr to rs1 |
693 |
|
* arg[1] = ptr to rs2 or an immediate value (int32_t) |
694 |
|
*/ |
695 |
|
X(return_imm) |
696 |
|
{ |
697 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page) |
698 |
|
/ sizeof(struct sparc_instr_call); |
699 |
|
cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) |
700 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
701 |
|
cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT); |
702 |
|
|
703 |
|
cpu->delay_slot = TO_BE_DELAYED; |
704 |
|
ic[1].f(cpu, ic+1); |
705 |
|
cpu->n_translated_instrs ++; |
706 |
|
|
707 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
708 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
709 |
|
cpu->delay_slot = NOT_DELAYED; |
710 |
|
cpu->pc = reg(ic->arg[0]) + (int32_t)ic->arg[1]; |
711 |
|
quick_pc_to_pointers(cpu); |
712 |
|
instr(restore)(cpu, ic); |
713 |
|
} else |
714 |
|
cpu->delay_slot = NOT_DELAYED; |
715 |
|
} |
716 |
|
X(return_reg) |
717 |
|
{ |
718 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page) |
719 |
|
/ sizeof(struct sparc_instr_call); |
720 |
|
cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) |
721 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
722 |
|
cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT); |
723 |
|
|
724 |
|
cpu->delay_slot = TO_BE_DELAYED; |
725 |
|
ic[1].f(cpu, ic+1); |
726 |
|
cpu->n_translated_instrs ++; |
727 |
|
|
728 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
729 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
730 |
|
cpu->delay_slot = NOT_DELAYED; |
731 |
|
cpu->pc = reg(ic->arg[0]) + reg(ic->arg[1]); |
732 |
|
quick_pc_to_pointers(cpu); |
733 |
|
instr(restore)(cpu, ic); |
734 |
|
} else |
735 |
|
cpu->delay_slot = NOT_DELAYED; |
736 |
|
} |
737 |
|
X(return_imm_trace) |
738 |
|
{ |
739 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page) |
740 |
|
/ sizeof(struct sparc_instr_call); |
741 |
|
cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) |
742 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
743 |
|
cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT); |
744 |
|
|
745 |
|
cpu->delay_slot = TO_BE_DELAYED; |
746 |
|
ic[1].f(cpu, ic+1); |
747 |
|
cpu->n_translated_instrs ++; |
748 |
|
|
749 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
750 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
751 |
|
cpu->delay_slot = NOT_DELAYED; |
752 |
|
cpu->pc = reg(ic->arg[0]) + (int32_t)ic->arg[1]; |
753 |
|
cpu_functioncall_trace(cpu, cpu->pc); |
754 |
|
quick_pc_to_pointers(cpu); |
755 |
|
instr(restore)(cpu, ic); |
756 |
|
} else |
757 |
|
cpu->delay_slot = NOT_DELAYED; |
758 |
|
} |
759 |
|
X(return_reg_trace) |
760 |
|
{ |
761 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page) |
762 |
|
/ sizeof(struct sparc_instr_call); |
763 |
|
cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) |
764 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
765 |
|
cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT); |
766 |
|
|
767 |
|
cpu->delay_slot = TO_BE_DELAYED; |
768 |
|
ic[1].f(cpu, ic+1); |
769 |
|
cpu->n_translated_instrs ++; |
770 |
|
|
771 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
772 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
773 |
|
cpu->delay_slot = NOT_DELAYED; |
774 |
|
cpu->pc = reg(ic->arg[0]) + reg(ic->arg[1]); |
775 |
|
cpu_functioncall_trace(cpu, cpu->pc); |
776 |
|
quick_pc_to_pointers(cpu); |
777 |
|
instr(restore)(cpu, ic); |
778 |
|
} else |
779 |
|
cpu->delay_slot = NOT_DELAYED; |
780 |
|
} |
781 |
|
|
782 |
|
|
783 |
|
/* |
784 |
* set: Set a register to a value (e.g. sethi). |
* set: Set a register to a value (e.g. sethi). |
785 |
* |
* |
786 |
* arg[0] = ptr to rd |
* arg[0] = ptr to rd |
803 |
X(add_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) + (int32_t)ic->arg[1]; } |
X(add_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) + (int32_t)ic->arg[1]; } |
804 |
X(and) { reg(ic->arg[2]) = reg(ic->arg[0]) & reg(ic->arg[1]); } |
X(and) { reg(ic->arg[2]) = reg(ic->arg[0]) & reg(ic->arg[1]); } |
805 |
X(and_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) & (int32_t)ic->arg[1]; } |
X(and_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) & (int32_t)ic->arg[1]; } |
806 |
|
X(andn) { reg(ic->arg[2]) = reg(ic->arg[0]) & ~reg(ic->arg[1]); } |
807 |
|
X(andn_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) & ~(int32_t)ic->arg[1]; } |
808 |
X(or) { reg(ic->arg[2]) = reg(ic->arg[0]) | reg(ic->arg[1]); } |
X(or) { reg(ic->arg[2]) = reg(ic->arg[0]) | reg(ic->arg[1]); } |
809 |
X(or_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) | (int32_t)ic->arg[1]; } |
X(or_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) | (int32_t)ic->arg[1]; } |
810 |
X(xor) { reg(ic->arg[2]) = reg(ic->arg[0]) ^ reg(ic->arg[1]); } |
X(xor) { reg(ic->arg[2]) = reg(ic->arg[0]) ^ reg(ic->arg[1]); } |
852 |
|
|
853 |
|
|
854 |
/* |
/* |
|
* Save: |
|
|
* |
|
|
* arg[0] = ptr to rs1 |
|
|
* arg[1] = ptr to rs2 or an immediate value (int32_t) |
|
|
* arg[2] = ptr to rd (_after_ the register window change) |
|
|
*/ |
|
|
X(save_v9_imm) |
|
|
{ |
|
|
MODE_uint_t rs = reg(ic->arg[0]) + (int32_t)ic->arg[1]; |
|
|
int cwp = cpu->cd.sparc.cwp; |
|
|
|
|
|
if (cpu->cd.sparc.cansave == 0) { |
|
|
fatal("save_v9_imm: spill trap. TODO\n"); |
|
|
exit(1); |
|
|
} |
|
|
|
|
|
if (cpu->cd.sparc.cleanwin - cpu->cd.sparc.canrestore == 0) { |
|
|
fatal("save_v9_imm: clean_window trap. TODO\n"); |
|
|
exit(1); |
|
|
} |
|
|
|
|
|
/* Save away old in registers: */ |
|
|
memcpy(&cpu->cd.sparc.r_inout[cwp][0], &cpu->cd.sparc.r[SPARC_REG_I0], |
|
|
sizeof(cpu->cd.sparc.r[SPARC_REG_I0]) * N_SPARC_INOUT_REG); |
|
|
|
|
|
/* Save away old local registers: */ |
|
|
memcpy(&cpu->cd.sparc.r_local[cwp][0], &cpu->cd.sparc.r[SPARC_REG_L0], |
|
|
sizeof(cpu->cd.sparc.r[SPARC_REG_L0]) * N_SPARC_INOUT_REG); |
|
|
|
|
|
cwp = cpu->cd.sparc.cwp = (cwp + 1) % cpu->cd.sparc.cpu_type.nwindows; |
|
|
cpu->cd.sparc.cansave --; |
|
|
cpu->cd.sparc.canrestore ++; /* TODO: modulo here too? */ |
|
|
|
|
|
/* The out registers become the new in registers: */ |
|
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_I0], &cpu->cd.sparc.r[SPARC_REG_O0], |
|
|
sizeof(cpu->cd.sparc.r[SPARC_REG_O0]) * N_SPARC_INOUT_REG); |
|
|
|
|
|
/* Read new local registers: */ |
|
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_L0], &cpu->cd.sparc.r_local[cwp][0], |
|
|
sizeof(cpu->cd.sparc.r[SPARC_REG_L0]) * N_SPARC_INOUT_REG); |
|
|
|
|
|
reg(ic->arg[2]) = rs; |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
855 |
* Add with ccr update: |
* Add with ccr update: |
856 |
* |
* |
857 |
* arg[0] = ptr to rs1 |
* arg[0] = ptr to rs1 |
1020 |
|
|
1021 |
|
|
1022 |
/* |
/* |
1023 |
|
* flushw: Flush Register Windows |
1024 |
|
*/ |
1025 |
|
X(flushw) |
1026 |
|
{ |
1027 |
|
/* flushw acts as a nop, if cansave = nwindows - 2: */ |
1028 |
|
if (cpu->cd.sparc.cansave == cpu->cd.sparc.cpu_type.nwindows - 2) |
1029 |
|
return; |
1030 |
|
|
1031 |
|
/* TODO */ |
1032 |
|
fatal("flushw: TODO: cansave = %i\n", cpu->cd.sparc.cansave); |
1033 |
|
exit(1); |
1034 |
|
} |
1035 |
|
|
1036 |
|
|
1037 |
|
/* |
1038 |
* rd: Read special register |
* rd: Read special register |
1039 |
* |
* |
1040 |
* arg[2] = ptr to rd |
* arg[2] = ptr to rd |
1092 |
{ |
{ |
1093 |
sparc_update_pstate(cpu, reg(ic->arg[0]) ^ (int32_t)ic->arg[1]); |
sparc_update_pstate(cpu, reg(ic->arg[0]) ^ (int32_t)ic->arg[1]); |
1094 |
} |
} |
1095 |
|
X(wrpr_cleanwin) |
1096 |
|
{ |
1097 |
|
cpu->cd.sparc.cleanwin = (uint32_t) (reg(ic->arg[0]) ^ reg(ic->arg[1])); |
1098 |
|
} |
1099 |
|
X(wrpr_cleanwin_imm) |
1100 |
|
{ |
1101 |
|
cpu->cd.sparc.cleanwin = |
1102 |
|
(uint32_t) (reg(ic->arg[0]) ^ (int32_t)ic->arg[1]); |
1103 |
|
} |
1104 |
|
|
1105 |
|
|
1106 |
/*****************************************************************************/ |
/*****************************************************************************/ |
1254 |
/* TODO: samepage */ |
/* TODO: samepage */ |
1255 |
switch (rd + (cc << 5)) { |
switch (rd + (cc << 5)) { |
1256 |
case 0x01: ic->f = instr(be); break; |
case 0x01: ic->f = instr(be); break; |
1257 |
|
case 0x02: ic->f = instr(ble); break; |
1258 |
case 0x03: ic->f = instr(bl); break; |
case 0x03: ic->f = instr(bl); break; |
1259 |
|
case 0x08: ic->f = instr(ba); break; |
1260 |
case 0x09: ic->f = instr(bne); break; |
case 0x09: ic->f = instr(bne); break; |
1261 |
case 0x0a: ic->f = instr(bg); break; |
case 0x0a: ic->f = instr(bg); break; |
1262 |
case 0x0b: ic->f = instr(bge); break; |
case 0x0b: ic->f = instr(bge); break; |
1263 |
case 0x19: ic->f = instr(bne_a); break; |
case 0x19: ic->f = instr(bne_a); break; |
1264 |
case 0x41: ic->f = instr(be_xcc); break; |
case 0x41: ic->f = instr(be_xcc); break; |
1265 |
|
case 0x42: ic->f = instr(ble_xcc);break; |
1266 |
case 0x43: ic->f = instr(bl_xcc); break; |
case 0x43: ic->f = instr(bl_xcc); break; |
1267 |
|
case 0x48: ic->f = instr(ba); break; |
1268 |
case 0x4a: ic->f = instr(bg_xcc); break; |
case 0x4a: ic->f = instr(bg_xcc); break; |
1269 |
case 0x4b: ic->f = instr(bge_xcc); break; |
case 0x4b: ic->f = instr(bge_xcc);break; |
1270 |
default:fatal("Unimplemented branch, 0x%x\n", |
default:fatal("Unimplemented branch, 0x%x\n", |
1271 |
rd + (cc<<5)); |
rd + (cc<<5)); |
1272 |
goto bad; |
goto bad; |
1284 |
case 0x01: ic->f = instr(be); break; |
case 0x01: ic->f = instr(be); break; |
1285 |
case 0x03: ic->f = instr(bl); break; |
case 0x03: ic->f = instr(bl); break; |
1286 |
case 0x08: ic->f = instr(ba); break; |
case 0x08: ic->f = instr(ba); break; |
1287 |
|
case 0x09: ic->f = instr(bne); break; |
1288 |
case 0x0b: ic->f = instr(bge); break; |
case 0x0b: ic->f = instr(bge); break; |
1289 |
default:fatal("Unimplemented branch rd=%i\n", rd); |
default:fatal("Unimplemented branch rd=%i\n", rd); |
1290 |
goto bad; |
goto bad; |
1337 |
case 2: /* or */ |
case 2: /* or */ |
1338 |
case 3: /* xor */ |
case 3: /* xor */ |
1339 |
case 4: /* sub */ |
case 4: /* sub */ |
1340 |
|
case 5: /* andn */ |
1341 |
case 14:/* udiv */ |
case 14:/* udiv */ |
1342 |
case 16:/* addcc */ |
case 16:/* addcc */ |
1343 |
case 17:/* andcc */ |
case 17:/* andcc */ |
1356 |
case 2: ic->f = instr(or_imm); break; |
case 2: ic->f = instr(or_imm); break; |
1357 |
case 3: ic->f = instr(xor_imm); break; |
case 3: ic->f = instr(xor_imm); break; |
1358 |
case 4: ic->f = instr(sub_imm); break; |
case 4: ic->f = instr(sub_imm); break; |
1359 |
|
case 5: ic->f = instr(andn_imm); break; |
1360 |
case 14:ic->f = instr(udiv_imm); break; |
case 14:ic->f = instr(udiv_imm); break; |
1361 |
case 16:ic->f = instr(addcc_imm); break; |
case 16:ic->f = instr(addcc_imm); break; |
1362 |
case 17:ic->f = instr(andcc_imm); break; |
case 17:ic->f = instr(andcc_imm); break; |
1403 |
case 2: ic->f = instr(or); break; |
case 2: ic->f = instr(or); break; |
1404 |
case 3: ic->f = instr(xor); break; |
case 3: ic->f = instr(xor); break; |
1405 |
case 4: ic->f = instr(sub); break; |
case 4: ic->f = instr(sub); break; |
1406 |
|
case 5: ic->f = instr(andn); break; |
1407 |
case 14:ic->f = instr(udiv); break; |
case 14:ic->f = instr(udiv); break; |
1408 |
case 16:ic->f = instr(addcc); break; |
case 16:ic->f = instr(addcc); break; |
1409 |
case 17:ic->f = instr(andcc); break; |
case 17:ic->f = instr(andcc); break; |
1487 |
} |
} |
1488 |
break; |
break; |
1489 |
|
|
1490 |
|
case 43:if (iword == 0x81580000) { |
1491 |
|
ic->f = instr(flushw); |
1492 |
|
} else { |
1493 |
|
fatal("Unimplemented iword=0x%08"PRIx32"\n", |
1494 |
|
iword); |
1495 |
|
goto bad; |
1496 |
|
} |
1497 |
|
break; |
1498 |
|
|
1499 |
case 48:/* wr (Note: works as xor) */ |
case 48:/* wr (Note: works as xor) */ |
1500 |
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
1501 |
if (use_imm) { |
if (use_imm) { |
1531 |
case 4: ic->f = instr(wrpr_tick_imm); break; |
case 4: ic->f = instr(wrpr_tick_imm); break; |
1532 |
case 6: ic->f = instr(wrpr_pstate_imm); break; |
case 6: ic->f = instr(wrpr_pstate_imm); break; |
1533 |
case 8: ic->f = instr(wrpr_pil_imm); break; |
case 8: ic->f = instr(wrpr_pil_imm); break; |
1534 |
|
case 12:ic->f = instr(wrpr_cleanwin_imm);break; |
1535 |
} |
} |
1536 |
} else { |
} else { |
1537 |
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs2]; |
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs2]; |
1539 |
case 4: ic->f = instr(wrpr_tick); break; |
case 4: ic->f = instr(wrpr_tick); break; |
1540 |
case 6: ic->f = instr(wrpr_pstate); break; |
case 6: ic->f = instr(wrpr_pstate); break; |
1541 |
case 8: ic->f = instr(wrpr_pil); break; |
case 8: ic->f = instr(wrpr_pil); break; |
1542 |
|
case 12:ic->f = instr(wrpr_cleanwin); break; |
1543 |
} |
} |
1544 |
} |
} |
1545 |
if (ic->f == NULL) { |
if (ic->f == NULL) { |
1582 |
} |
} |
1583 |
break; |
break; |
1584 |
|
|
1585 |
|
case 57:/* return */ |
1586 |
|
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
1587 |
|
|
1588 |
|
if (use_imm) { |
1589 |
|
ic->arg[1] = siconst; |
1590 |
|
ic->f = instr(return_imm); |
1591 |
|
} else { |
1592 |
|
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs2]; |
1593 |
|
ic->f = instr(return_reg); |
1594 |
|
} |
1595 |
|
|
1596 |
|
/* special trace case: */ |
1597 |
|
if (cpu->machine->show_trace_tree) { |
1598 |
|
if (use_imm) |
1599 |
|
ic->f = instr(return_imm_trace); |
1600 |
|
else |
1601 |
|
ic->f = instr(return_reg_trace); |
1602 |
|
} |
1603 |
|
break; |
1604 |
|
|
1605 |
default:fatal("TODO: unimplemented op2=%i for main " |
default:fatal("TODO: unimplemented op2=%i for main " |
1606 |
"opcode %i\n", op2, main_opcode); |
"opcode %i\n", op2, main_opcode); |
1607 |
goto bad; |
goto bad; |