1 |
/* |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_sparc_instr.c,v 1.18 2006/05/17 20:27:31 debug Exp $ |
* $Id: cpu_sparc_instr.c,v 1.26 2006/12/30 13:30:55 debug Exp $ |
29 |
* |
* |
30 |
* SPARC instructions. |
* SPARC instructions. |
31 |
* |
* |
37 |
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|
38 |
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39 |
/* |
/* |
40 |
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* invalid: For catching bugs. |
41 |
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*/ |
42 |
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X(invalid) |
43 |
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{ |
44 |
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fatal("FATAL ERROR: An internal error occured in the SPARC" |
45 |
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" dyntrans code. Please contact the author with detailed" |
46 |
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" repro steps on how to trigger this bug.\n"); |
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exit(1); |
48 |
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} |
49 |
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50 |
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|
51 |
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/* |
52 |
* nop: Do nothing. |
* nop: Do nothing. |
53 |
*/ |
*/ |
54 |
X(nop) |
X(nop) |
106 |
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107 |
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108 |
/* |
/* |
109 |
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* bl |
110 |
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* |
111 |
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* arg[0] = int32_t displacement compared to the start of the current page |
112 |
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*/ |
113 |
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X(bl) |
114 |
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{ |
115 |
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MODE_uint_t old_pc = cpu->pc; |
116 |
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int n = (cpu->cd.sparc.ccr & SPARC_CCR_N) ? 1 : 0; |
117 |
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int v = (cpu->cd.sparc.ccr & SPARC_CCR_V) ? 1 : 0; |
118 |
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int cond = n ^ v; |
119 |
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cpu->delay_slot = TO_BE_DELAYED; |
120 |
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ic[1].f(cpu, ic+1); |
121 |
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cpu->n_translated_instrs ++; |
122 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
123 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
124 |
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cpu->delay_slot = NOT_DELAYED; |
125 |
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if (cond) { |
126 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
127 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
128 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
129 |
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quick_pc_to_pointers(cpu); |
130 |
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} |
131 |
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} else |
132 |
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cpu->delay_slot = NOT_DELAYED; |
133 |
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} |
134 |
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X(bl_xcc) |
135 |
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{ |
136 |
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MODE_uint_t old_pc = cpu->pc; |
137 |
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int n = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_N)? 1:0; |
138 |
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int v = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_V)? 1:0; |
139 |
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int cond = n ^ v; |
140 |
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cpu->delay_slot = TO_BE_DELAYED; |
141 |
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ic[1].f(cpu, ic+1); |
142 |
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cpu->n_translated_instrs ++; |
143 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
144 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
145 |
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cpu->delay_slot = NOT_DELAYED; |
146 |
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if (cond) { |
147 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
148 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
149 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
150 |
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quick_pc_to_pointers(cpu); |
151 |
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} |
152 |
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} else |
153 |
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cpu->delay_slot = NOT_DELAYED; |
154 |
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} |
155 |
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156 |
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157 |
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/* |
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* ble |
159 |
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* |
160 |
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* arg[0] = int32_t displacement compared to the start of the current page |
161 |
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*/ |
162 |
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X(ble) |
163 |
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{ |
164 |
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MODE_uint_t old_pc = cpu->pc; |
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int n = (cpu->cd.sparc.ccr & SPARC_CCR_N) ? 1 : 0; |
166 |
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int v = (cpu->cd.sparc.ccr & SPARC_CCR_V) ? 1 : 0; |
167 |
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int z = (cpu->cd.sparc.ccr & SPARC_CCR_Z) ? 1 : 0; |
168 |
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int cond = (n ^ v) || z; |
169 |
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cpu->delay_slot = TO_BE_DELAYED; |
170 |
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ic[1].f(cpu, ic+1); |
171 |
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cpu->n_translated_instrs ++; |
172 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
173 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
174 |
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cpu->delay_slot = NOT_DELAYED; |
175 |
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if (cond) { |
176 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
177 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
178 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
179 |
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quick_pc_to_pointers(cpu); |
180 |
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} |
181 |
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} else |
182 |
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cpu->delay_slot = NOT_DELAYED; |
183 |
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} |
184 |
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X(ble_xcc) |
185 |
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{ |
186 |
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MODE_uint_t old_pc = cpu->pc; |
187 |
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int n = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_N)? 1:0; |
188 |
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int v = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_V)? 1:0; |
189 |
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int z = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_Z)? 1:0; |
190 |
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int cond = (n ^ v) || z; |
191 |
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cpu->delay_slot = TO_BE_DELAYED; |
192 |
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ic[1].f(cpu, ic+1); |
193 |
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cpu->n_translated_instrs ++; |
194 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
195 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
196 |
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cpu->delay_slot = NOT_DELAYED; |
197 |
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if (cond) { |
198 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
199 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
200 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
201 |
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quick_pc_to_pointers(cpu); |
202 |
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} |
203 |
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} else |
204 |
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cpu->delay_slot = NOT_DELAYED; |
205 |
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} |
206 |
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207 |
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208 |
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/* |
209 |
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* bne |
210 |
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* |
211 |
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* arg[0] = int32_t displacement compared to the start of the current page |
212 |
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*/ |
213 |
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X(bne) |
214 |
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{ |
215 |
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MODE_uint_t old_pc = cpu->pc; |
216 |
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int cond = (cpu->cd.sparc.ccr & SPARC_CCR_Z) ? 0 : 1; |
217 |
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cpu->delay_slot = TO_BE_DELAYED; |
218 |
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ic[1].f(cpu, ic+1); |
219 |
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cpu->n_translated_instrs ++; |
220 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
221 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
222 |
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cpu->delay_slot = NOT_DELAYED; |
223 |
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if (cond) { |
224 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
225 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
226 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
227 |
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quick_pc_to_pointers(cpu); |
228 |
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} |
229 |
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} else |
230 |
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cpu->delay_slot = NOT_DELAYED; |
231 |
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} |
232 |
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X(bne_a) |
233 |
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{ |
234 |
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MODE_uint_t old_pc = cpu->pc; |
235 |
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int cond = (cpu->cd.sparc.ccr & SPARC_CCR_Z) ? 0 : 1; |
236 |
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cpu->delay_slot = TO_BE_DELAYED; |
237 |
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if (!cond) { |
238 |
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/* Nullify the delay slot: */ |
239 |
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cpu->cd.sparc.next_ic ++; |
240 |
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return; |
241 |
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} |
242 |
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ic[1].f(cpu, ic+1); |
243 |
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cpu->n_translated_instrs ++; |
244 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
245 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
246 |
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cpu->delay_slot = NOT_DELAYED; |
247 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
248 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
249 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
250 |
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quick_pc_to_pointers(cpu); |
251 |
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} else |
252 |
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cpu->delay_slot = NOT_DELAYED; |
253 |
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} |
254 |
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|
255 |
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|
256 |
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/* |
257 |
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* bg |
258 |
|
* |
259 |
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* arg[0] = int32_t displacement compared to the start of the current page |
260 |
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*/ |
261 |
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X(bg) |
262 |
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{ |
263 |
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MODE_uint_t old_pc = cpu->pc; |
264 |
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int n = (cpu->cd.sparc.ccr & SPARC_CCR_N) ? 1 : 0; |
265 |
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int v = (cpu->cd.sparc.ccr & SPARC_CCR_V) ? 1 : 0; |
266 |
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int z = (cpu->cd.sparc.ccr & SPARC_CCR_Z) ? 1 : 0; |
267 |
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int cond = !(z | (n ^ v)); |
268 |
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cpu->delay_slot = TO_BE_DELAYED; |
269 |
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ic[1].f(cpu, ic+1); |
270 |
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cpu->n_translated_instrs ++; |
271 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
272 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
273 |
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cpu->delay_slot = NOT_DELAYED; |
274 |
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if (cond) { |
275 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
276 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
277 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
278 |
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quick_pc_to_pointers(cpu); |
279 |
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} |
280 |
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} else |
281 |
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cpu->delay_slot = NOT_DELAYED; |
282 |
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} |
283 |
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X(bg_xcc) |
284 |
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{ |
285 |
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MODE_uint_t old_pc = cpu->pc; |
286 |
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int n = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_N)? 1:0; |
287 |
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int v = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_V)? 1:0; |
288 |
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int z = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_Z)? 1:0; |
289 |
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int cond = !(z | (n ^ v)); |
290 |
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cpu->delay_slot = TO_BE_DELAYED; |
291 |
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ic[1].f(cpu, ic+1); |
292 |
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cpu->n_translated_instrs ++; |
293 |
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if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
294 |
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/* Note: Must be non-delayed when jumping to the new pc: */ |
295 |
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cpu->delay_slot = NOT_DELAYED; |
296 |
|
if (cond) { |
297 |
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old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
298 |
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<< SPARC_INSTR_ALIGNMENT_SHIFT); |
299 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
300 |
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quick_pc_to_pointers(cpu); |
301 |
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} |
302 |
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} else |
303 |
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cpu->delay_slot = NOT_DELAYED; |
304 |
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} |
305 |
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|
306 |
|
|
307 |
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/* |
308 |
|
* bge |
309 |
|
* |
310 |
|
* arg[0] = int32_t displacement compared to the start of the current page |
311 |
|
*/ |
312 |
|
X(bge) |
313 |
|
{ |
314 |
|
MODE_uint_t old_pc = cpu->pc; |
315 |
|
int n = (cpu->cd.sparc.ccr & SPARC_CCR_N) ? 1 : 0; |
316 |
|
int v = (cpu->cd.sparc.ccr & SPARC_CCR_V) ? 1 : 0; |
317 |
|
int cond = !(n ^ v); |
318 |
|
cpu->delay_slot = TO_BE_DELAYED; |
319 |
|
ic[1].f(cpu, ic+1); |
320 |
|
cpu->n_translated_instrs ++; |
321 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
322 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
323 |
|
cpu->delay_slot = NOT_DELAYED; |
324 |
|
if (cond) { |
325 |
|
old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
326 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
327 |
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cpu->pc = old_pc + (int32_t)ic->arg[0]; |
328 |
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quick_pc_to_pointers(cpu); |
329 |
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} |
330 |
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} else |
331 |
|
cpu->delay_slot = NOT_DELAYED; |
332 |
|
} |
333 |
|
X(bge_xcc) |
334 |
|
{ |
335 |
|
MODE_uint_t old_pc = cpu->pc; |
336 |
|
int n = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_N)? 1:0; |
337 |
|
int v = ((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_V)? 1:0; |
338 |
|
int cond = !(n ^ v); |
339 |
|
cpu->delay_slot = TO_BE_DELAYED; |
340 |
|
ic[1].f(cpu, ic+1); |
341 |
|
cpu->n_translated_instrs ++; |
342 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
343 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
344 |
|
cpu->delay_slot = NOT_DELAYED; |
345 |
|
if (cond) { |
346 |
|
old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
347 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
348 |
|
cpu->pc = old_pc + (int32_t)ic->arg[0]; |
349 |
|
quick_pc_to_pointers(cpu); |
350 |
|
} |
351 |
|
} else |
352 |
|
cpu->delay_slot = NOT_DELAYED; |
353 |
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} |
354 |
|
|
355 |
|
|
356 |
|
/* |
357 |
|
* be |
358 |
|
* |
359 |
|
* arg[0] = int32_t displacement compared to the start of the current page |
360 |
|
*/ |
361 |
|
X(be) |
362 |
|
{ |
363 |
|
MODE_uint_t old_pc = cpu->pc; |
364 |
|
int cond = cpu->cd.sparc.ccr & SPARC_CCR_Z; |
365 |
|
cpu->delay_slot = TO_BE_DELAYED; |
366 |
|
ic[1].f(cpu, ic+1); |
367 |
|
cpu->n_translated_instrs ++; |
368 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
369 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
370 |
|
cpu->delay_slot = NOT_DELAYED; |
371 |
|
if (cond) { |
372 |
|
old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
373 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
374 |
|
cpu->pc = old_pc + (int32_t)ic->arg[0]; |
375 |
|
quick_pc_to_pointers(cpu); |
376 |
|
} |
377 |
|
} else |
378 |
|
cpu->delay_slot = NOT_DELAYED; |
379 |
|
} |
380 |
|
X(be_xcc) |
381 |
|
{ |
382 |
|
MODE_uint_t old_pc = cpu->pc; |
383 |
|
int cond = (cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) & SPARC_CCR_Z; |
384 |
|
cpu->delay_slot = TO_BE_DELAYED; |
385 |
|
ic[1].f(cpu, ic+1); |
386 |
|
cpu->n_translated_instrs ++; |
387 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
388 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
389 |
|
cpu->delay_slot = NOT_DELAYED; |
390 |
|
if (cond) { |
391 |
|
old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
392 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
393 |
|
cpu->pc = old_pc + (int32_t)ic->arg[0]; |
394 |
|
quick_pc_to_pointers(cpu); |
395 |
|
} |
396 |
|
} else |
397 |
|
cpu->delay_slot = NOT_DELAYED; |
398 |
|
} |
399 |
|
|
400 |
|
|
401 |
|
/* |
402 |
* ba |
* ba |
403 |
* |
* |
404 |
* arg[0] = int32_t displacement compared to the start of the current page |
* arg[0] = int32_t displacement compared to the start of the current page |
422 |
|
|
423 |
|
|
424 |
/* |
/* |
425 |
|
* brnz |
426 |
|
* |
427 |
|
* arg[0] = int32_t displacement compared to the start of the current page |
428 |
|
* arg[1] = ptr to rs1 |
429 |
|
*/ |
430 |
|
X(brnz) |
431 |
|
{ |
432 |
|
MODE_uint_t old_pc = cpu->pc; |
433 |
|
int cond = reg(ic->arg[1]) != 0; |
434 |
|
cpu->delay_slot = TO_BE_DELAYED; |
435 |
|
ic[1].f(cpu, ic+1); |
436 |
|
cpu->n_translated_instrs ++; |
437 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
438 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
439 |
|
cpu->delay_slot = NOT_DELAYED; |
440 |
|
if (cond) { |
441 |
|
old_pc &= ~((SPARC_IC_ENTRIES_PER_PAGE - 1) |
442 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
443 |
|
cpu->pc = old_pc + (int32_t)ic->arg[0]; |
444 |
|
quick_pc_to_pointers(cpu); |
445 |
|
} |
446 |
|
} else |
447 |
|
cpu->delay_slot = NOT_DELAYED; |
448 |
|
} |
449 |
|
|
450 |
|
|
451 |
|
/* |
452 |
|
* Save: |
453 |
|
* |
454 |
|
* arg[0] = ptr to rs1 |
455 |
|
* arg[1] = ptr to rs2 or an immediate value (int32_t) |
456 |
|
* arg[2] = ptr to rd (_after_ the register window change) |
457 |
|
*/ |
458 |
|
X(save_v9_imm) |
459 |
|
{ |
460 |
|
MODE_uint_t rs = reg(ic->arg[0]) + (int32_t)ic->arg[1]; |
461 |
|
int cwp = cpu->cd.sparc.cwp; |
462 |
|
|
463 |
|
if (cpu->cd.sparc.cansave == 0) { |
464 |
|
fatal("save_v9_imm: spill trap. TODO\n"); |
465 |
|
exit(1); |
466 |
|
} |
467 |
|
|
468 |
|
if (cpu->cd.sparc.cleanwin - cpu->cd.sparc.canrestore == 0) { |
469 |
|
fatal("save_v9_imm: clean_window trap. TODO\n"); |
470 |
|
exit(1); |
471 |
|
} |
472 |
|
|
473 |
|
/* Save away old in registers: */ |
474 |
|
memcpy(&cpu->cd.sparc.r_inout[cwp][0], &cpu->cd.sparc.r[SPARC_REG_I0], |
475 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_I0]) * N_SPARC_INOUT_REG); |
476 |
|
|
477 |
|
/* Save away old local registers: */ |
478 |
|
memcpy(&cpu->cd.sparc.r_local[cwp][0], &cpu->cd.sparc.r[SPARC_REG_L0], |
479 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_L0]) * N_SPARC_INOUT_REG); |
480 |
|
|
481 |
|
cpu->cd.sparc.cwp = (cwp + 1) % cpu->cd.sparc.cpu_type.nwindows; |
482 |
|
cpu->cd.sparc.cansave --; |
483 |
|
cpu->cd.sparc.canrestore ++; /* TODO: modulo here too? */ |
484 |
|
cwp = cpu->cd.sparc.cwp; |
485 |
|
|
486 |
|
/* The out registers become the new in registers: */ |
487 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_I0], &cpu->cd.sparc.r[SPARC_REG_O0], |
488 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_O0]) * N_SPARC_INOUT_REG); |
489 |
|
|
490 |
|
/* Read new local registers: */ |
491 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_L0], &cpu->cd.sparc.r_local[cwp][0], |
492 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_L0]) * N_SPARC_INOUT_REG); |
493 |
|
|
494 |
|
reg(ic->arg[2]) = rs; |
495 |
|
} |
496 |
|
|
497 |
|
|
498 |
|
/* |
499 |
|
* Restore: |
500 |
|
*/ |
501 |
|
X(restore) |
502 |
|
{ |
503 |
|
int cwp = cpu->cd.sparc.cwp; |
504 |
|
|
505 |
|
if (cpu->cd.sparc.canrestore == 0) { |
506 |
|
fatal("restore: spill trap. TODO\n"); |
507 |
|
exit(1); |
508 |
|
} |
509 |
|
|
510 |
|
cpu->cd.sparc.cwp = cwp - 1; |
511 |
|
if (cwp == 0) |
512 |
|
cpu->cd.sparc.cwp = cpu->cd.sparc.cpu_type.nwindows - 1; |
513 |
|
cpu->cd.sparc.cansave ++; |
514 |
|
cpu->cd.sparc.canrestore --; |
515 |
|
cwp = cpu->cd.sparc.cwp; |
516 |
|
|
517 |
|
/* The in registers become the new out registers: */ |
518 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_O0], &cpu->cd.sparc.r[SPARC_REG_I0], |
519 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_O0]) * N_SPARC_INOUT_REG); |
520 |
|
|
521 |
|
/* Read back the local registers: */ |
522 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_L0], &cpu->cd.sparc.r_local[cwp][0], |
523 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_L0]) * N_SPARC_INOUT_REG); |
524 |
|
|
525 |
|
/* Read back the in registers: */ |
526 |
|
memcpy(&cpu->cd.sparc.r[SPARC_REG_I0], &cpu->cd.sparc.r_inout[cwp][0], |
527 |
|
sizeof(cpu->cd.sparc.r[SPARC_REG_I0]) * N_SPARC_INOUT_REG); |
528 |
|
} |
529 |
|
|
530 |
|
|
531 |
|
/* |
532 |
* Jump and link |
* Jump and link |
533 |
* |
* |
534 |
* arg[0] = ptr to rs1 |
* arg[0] = ptr to rs1 |
687 |
|
|
688 |
|
|
689 |
/* |
/* |
690 |
|
* Return |
691 |
|
* |
692 |
|
* arg[0] = ptr to rs1 |
693 |
|
* arg[1] = ptr to rs2 or an immediate value (int32_t) |
694 |
|
*/ |
695 |
|
X(return_imm) |
696 |
|
{ |
697 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page) |
698 |
|
/ sizeof(struct sparc_instr_call); |
699 |
|
cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) |
700 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
701 |
|
cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT); |
702 |
|
|
703 |
|
cpu->delay_slot = TO_BE_DELAYED; |
704 |
|
ic[1].f(cpu, ic+1); |
705 |
|
cpu->n_translated_instrs ++; |
706 |
|
|
707 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
708 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
709 |
|
cpu->delay_slot = NOT_DELAYED; |
710 |
|
cpu->pc = reg(ic->arg[0]) + (int32_t)ic->arg[1]; |
711 |
|
quick_pc_to_pointers(cpu); |
712 |
|
instr(restore)(cpu, ic); |
713 |
|
} else |
714 |
|
cpu->delay_slot = NOT_DELAYED; |
715 |
|
} |
716 |
|
X(return_reg) |
717 |
|
{ |
718 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page) |
719 |
|
/ sizeof(struct sparc_instr_call); |
720 |
|
cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) |
721 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
722 |
|
cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT); |
723 |
|
|
724 |
|
cpu->delay_slot = TO_BE_DELAYED; |
725 |
|
ic[1].f(cpu, ic+1); |
726 |
|
cpu->n_translated_instrs ++; |
727 |
|
|
728 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
729 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
730 |
|
cpu->delay_slot = NOT_DELAYED; |
731 |
|
cpu->pc = reg(ic->arg[0]) + reg(ic->arg[1]); |
732 |
|
quick_pc_to_pointers(cpu); |
733 |
|
instr(restore)(cpu, ic); |
734 |
|
} else |
735 |
|
cpu->delay_slot = NOT_DELAYED; |
736 |
|
} |
737 |
|
X(return_imm_trace) |
738 |
|
{ |
739 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page) |
740 |
|
/ sizeof(struct sparc_instr_call); |
741 |
|
cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) |
742 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
743 |
|
cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT); |
744 |
|
|
745 |
|
cpu->delay_slot = TO_BE_DELAYED; |
746 |
|
ic[1].f(cpu, ic+1); |
747 |
|
cpu->n_translated_instrs ++; |
748 |
|
|
749 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
750 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
751 |
|
cpu->delay_slot = NOT_DELAYED; |
752 |
|
cpu->pc = reg(ic->arg[0]) + (int32_t)ic->arg[1]; |
753 |
|
cpu_functioncall_trace(cpu, cpu->pc); |
754 |
|
quick_pc_to_pointers(cpu); |
755 |
|
instr(restore)(cpu, ic); |
756 |
|
} else |
757 |
|
cpu->delay_slot = NOT_DELAYED; |
758 |
|
} |
759 |
|
X(return_reg_trace) |
760 |
|
{ |
761 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page) |
762 |
|
/ sizeof(struct sparc_instr_call); |
763 |
|
cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) |
764 |
|
<< SPARC_INSTR_ALIGNMENT_SHIFT); |
765 |
|
cpu->pc += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT); |
766 |
|
|
767 |
|
cpu->delay_slot = TO_BE_DELAYED; |
768 |
|
ic[1].f(cpu, ic+1); |
769 |
|
cpu->n_translated_instrs ++; |
770 |
|
|
771 |
|
if (!(cpu->delay_slot & EXCEPTION_IN_DELAY_SLOT)) { |
772 |
|
/* Note: Must be non-delayed when jumping to the new pc: */ |
773 |
|
cpu->delay_slot = NOT_DELAYED; |
774 |
|
cpu->pc = reg(ic->arg[0]) + reg(ic->arg[1]); |
775 |
|
cpu_functioncall_trace(cpu, cpu->pc); |
776 |
|
quick_pc_to_pointers(cpu); |
777 |
|
instr(restore)(cpu, ic); |
778 |
|
} else |
779 |
|
cpu->delay_slot = NOT_DELAYED; |
780 |
|
} |
781 |
|
|
782 |
|
|
783 |
|
/* |
784 |
* set: Set a register to a value (e.g. sethi). |
* set: Set a register to a value (e.g. sethi). |
785 |
* |
* |
786 |
* arg[0] = ptr to rd |
* arg[0] = ptr to rd |
803 |
X(add_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) + (int32_t)ic->arg[1]; } |
X(add_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) + (int32_t)ic->arg[1]; } |
804 |
X(and) { reg(ic->arg[2]) = reg(ic->arg[0]) & reg(ic->arg[1]); } |
X(and) { reg(ic->arg[2]) = reg(ic->arg[0]) & reg(ic->arg[1]); } |
805 |
X(and_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) & (int32_t)ic->arg[1]; } |
X(and_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) & (int32_t)ic->arg[1]; } |
806 |
|
X(andn) { reg(ic->arg[2]) = reg(ic->arg[0]) & ~reg(ic->arg[1]); } |
807 |
|
X(andn_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) & ~(int32_t)ic->arg[1]; } |
808 |
X(or) { reg(ic->arg[2]) = reg(ic->arg[0]) | reg(ic->arg[1]); } |
X(or) { reg(ic->arg[2]) = reg(ic->arg[0]) | reg(ic->arg[1]); } |
809 |
X(or_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) | (int32_t)ic->arg[1]; } |
X(or_imm) { reg(ic->arg[2]) = reg(ic->arg[0]) | (int32_t)ic->arg[1]; } |
810 |
X(xor) { reg(ic->arg[2]) = reg(ic->arg[0]) ^ reg(ic->arg[1]); } |
X(xor) { reg(ic->arg[2]) = reg(ic->arg[0]) ^ reg(ic->arg[1]); } |
833 |
X(sra_imm) { reg(ic->arg[2]) = (int32_t)reg(ic->arg[0]) >> ic->arg[1]; } |
X(sra_imm) { reg(ic->arg[2]) = (int32_t)reg(ic->arg[0]) >> ic->arg[1]; } |
834 |
X(srax_imm) { reg(ic->arg[2]) = (int64_t)reg(ic->arg[0]) >> ic->arg[1]; } |
X(srax_imm) { reg(ic->arg[2]) = (int64_t)reg(ic->arg[0]) >> ic->arg[1]; } |
835 |
|
|
836 |
|
X(udiv) |
837 |
|
{ |
838 |
|
uint64_t z = (cpu->cd.sparc.y << 32) | (uint32_t)reg(ic->arg[0]); |
839 |
|
z /= (uint32_t)reg(ic->arg[1]); |
840 |
|
if (z > 0xffffffff) |
841 |
|
z = 0xffffffff; |
842 |
|
reg(ic->arg[2]) = z; |
843 |
|
} |
844 |
|
X(udiv_imm) |
845 |
|
{ |
846 |
|
uint64_t z = (cpu->cd.sparc.y << 32) | (uint32_t)reg(ic->arg[0]); |
847 |
|
z /= (uint32_t)ic->arg[1]; |
848 |
|
if (z > 0xffffffff) |
849 |
|
z = 0xffffffff; |
850 |
|
reg(ic->arg[2]) = z; |
851 |
|
} |
852 |
|
|
853 |
|
|
854 |
|
/* |
855 |
|
* Add with ccr update: |
856 |
|
* |
857 |
|
* arg[0] = ptr to rs1 |
858 |
|
* arg[1] = ptr to rs2 or an immediate value (int32_t) |
859 |
|
* arg[2] = ptr to rd |
860 |
|
*/ |
861 |
|
int32_t sparc_addcc32(struct cpu *cpu, int32_t rs1, int32_t rs2); |
862 |
|
#ifdef MODE32 |
863 |
|
int32_t sparc_addcc32(struct cpu *cpu, int32_t rs1, int32_t rs2) |
864 |
|
#else |
865 |
|
int64_t sparc_addcc64(struct cpu *cpu, int64_t rs1, int64_t rs2) |
866 |
|
#endif |
867 |
|
{ |
868 |
|
int cc = 0, sign1 = 0, sign2 = 0, signd = 0, mask = SPARC_CCR_ICC_MASK; |
869 |
|
MODE_int_t rd = rs1 + rs2; |
870 |
|
if (rd == 0) |
871 |
|
cc = SPARC_CCR_Z; |
872 |
|
else if (rd < 0) |
873 |
|
cc = SPARC_CCR_N, signd = 1; |
874 |
|
if (rs1 < 0) |
875 |
|
sign1 = 1; |
876 |
|
if (rs2 < 0) |
877 |
|
sign2 = 1; |
878 |
|
if (sign1 == sign2 && sign1 != signd) |
879 |
|
cc |= SPARC_CCR_V; |
880 |
|
/* TODO: SPARC_CCR_C */ |
881 |
|
#ifndef MODE32 |
882 |
|
mask <<= SPARC_CCR_XCC_SHIFT; |
883 |
|
cc <<= SPARC_CCR_XCC_SHIFT; |
884 |
|
#endif |
885 |
|
cpu->cd.sparc.ccr &= ~mask; |
886 |
|
cpu->cd.sparc.ccr |= cc; |
887 |
|
return rd; |
888 |
|
} |
889 |
|
X(addcc) |
890 |
|
{ |
891 |
|
/* Like add, but updates the ccr, and does both 32-bit and |
892 |
|
64-bit comparison at the same time. */ |
893 |
|
MODE_int_t rs1 = reg(ic->arg[0]), rs2 = reg(ic->arg[1]), rd; |
894 |
|
rd = sparc_addcc32(cpu, rs1, rs2); |
895 |
|
#ifndef MODE32 |
896 |
|
rd = sparc_addcc64(cpu, rs1, rs2); |
897 |
|
#endif |
898 |
|
reg(ic->arg[2]) = rd; |
899 |
|
} |
900 |
|
X(addcc_imm) |
901 |
|
{ |
902 |
|
MODE_int_t rs1 = reg(ic->arg[0]), rs2 = (int32_t)ic->arg[1], rd; |
903 |
|
rd = sparc_addcc32(cpu, rs1, rs2); |
904 |
|
#ifndef MODE32 |
905 |
|
rd = sparc_addcc64(cpu, rs1, rs2); |
906 |
|
#endif |
907 |
|
reg(ic->arg[2]) = rd; |
908 |
|
} |
909 |
|
|
910 |
|
|
911 |
|
/* |
912 |
|
* And with ccr update: |
913 |
|
* |
914 |
|
* arg[0] = ptr to rs1 |
915 |
|
* arg[1] = ptr to rs2 or an immediate value (int32_t) |
916 |
|
* arg[2] = ptr to rd |
917 |
|
*/ |
918 |
|
int32_t sparc_andcc32(struct cpu *cpu, int32_t rs1, int32_t rs2); |
919 |
|
#ifdef MODE32 |
920 |
|
int32_t sparc_andcc32(struct cpu *cpu, int32_t rs1, int32_t rs2) |
921 |
|
#else |
922 |
|
int64_t sparc_andcc64(struct cpu *cpu, int64_t rs1, int64_t rs2) |
923 |
|
#endif |
924 |
|
{ |
925 |
|
int cc = 0, mask = SPARC_CCR_ICC_MASK; |
926 |
|
MODE_int_t rd = rs1 & rs2; |
927 |
|
if (rd == 0) |
928 |
|
cc = SPARC_CCR_Z; |
929 |
|
else if (rd < 0) |
930 |
|
cc = SPARC_CCR_N; |
931 |
|
/* Note: SPARC_CCR_C and SPARC_CCR_V are always zero. */ |
932 |
|
#ifndef MODE32 |
933 |
|
mask <<= SPARC_CCR_XCC_SHIFT; |
934 |
|
cc <<= SPARC_CCR_XCC_SHIFT; |
935 |
|
#endif |
936 |
|
cpu->cd.sparc.ccr &= ~mask; |
937 |
|
cpu->cd.sparc.ccr |= cc; |
938 |
|
return rd; |
939 |
|
} |
940 |
|
X(andcc) |
941 |
|
{ |
942 |
|
/* Like and, but updates the ccr, and does both 32-bit and |
943 |
|
64-bit comparison at the same time. */ |
944 |
|
MODE_int_t rs1 = reg(ic->arg[0]), rs2 = reg(ic->arg[1]), rd; |
945 |
|
rd = sparc_andcc32(cpu, rs1, rs2); |
946 |
|
#ifndef MODE32 |
947 |
|
rd = sparc_andcc64(cpu, rs1, rs2); |
948 |
|
#endif |
949 |
|
reg(ic->arg[2]) = rd; |
950 |
|
} |
951 |
|
X(andcc_imm) |
952 |
|
{ |
953 |
|
MODE_int_t rs1 = reg(ic->arg[0]), rs2 = (int32_t)ic->arg[1], rd; |
954 |
|
rd = sparc_andcc32(cpu, rs1, rs2); |
955 |
|
#ifndef MODE32 |
956 |
|
rd = sparc_andcc64(cpu, rs1, rs2); |
957 |
|
#endif |
958 |
|
reg(ic->arg[2]) = rd; |
959 |
|
} |
960 |
|
|
961 |
|
|
962 |
/* |
/* |
963 |
* Subtract with ccr update: |
* Subtract with ccr update: |
1016 |
} |
} |
1017 |
|
|
1018 |
|
|
1019 |
|
#include "tmp_sparc_loadstore.c" |
1020 |
|
|
1021 |
|
|
1022 |
/* |
/* |
1023 |
* rd: Read special register: |
* rd: Read special register |
1024 |
* |
* |
1025 |
* arg[2] = ptr to rd |
* arg[2] = ptr to rd |
1026 |
*/ |
*/ |
1031 |
|
|
1032 |
|
|
1033 |
/* |
/* |
1034 |
|
* rdpr: Read privileged register |
1035 |
|
* |
1036 |
|
* arg[2] = ptr to rd |
1037 |
|
*/ |
1038 |
|
X(rdpr_tba) |
1039 |
|
{ |
1040 |
|
reg(ic->arg[2]) = cpu->cd.sparc.tba; |
1041 |
|
} |
1042 |
|
X(rdpr_ver) |
1043 |
|
{ |
1044 |
|
reg(ic->arg[2]) = cpu->cd.sparc.ver; |
1045 |
|
} |
1046 |
|
|
1047 |
|
|
1048 |
|
/* |
1049 |
* wrpr: Write to privileged register |
* wrpr: Write to privileged register |
1050 |
* |
* |
1051 |
* arg[0] = ptr to rs1 |
* arg[0] = ptr to rs1 |
1134 |
X(to_be_translated) |
X(to_be_translated) |
1135 |
{ |
{ |
1136 |
MODE_uint_t addr; |
MODE_uint_t addr; |
1137 |
int low_pc; |
int low_pc, in_crosspage_delayslot = 0; |
|
int in_crosspage_delayslot = 0; |
|
1138 |
uint32_t iword; |
uint32_t iword; |
1139 |
unsigned char *page; |
unsigned char *page; |
1140 |
unsigned char ib[4]; |
unsigned char ib[4]; |
1141 |
int main_opcode, op2, rd, rs1, rs2, btype, asi, cc, p, use_imm, x64 = 0; |
int main_opcode, op2, rd, rs1, rs2, btype, asi, cc, p, use_imm, x64 = 0; |
1142 |
|
int store, signedness, size; |
1143 |
int32_t tmpi32, siconst; |
int32_t tmpi32, siconst; |
1144 |
/* void (*samepage_function)(struct cpu *, struct sparc_instr_call *);*/ |
/* void (*samepage_function)(struct cpu *, struct sparc_instr_call *);*/ |
1145 |
|
|
1221 |
|
|
1222 |
case 0: switch (op2) { |
case 0: switch (op2) { |
1223 |
|
|
1224 |
|
case 1: /* branch (icc or xcc) */ |
1225 |
|
tmpi32 = (iword << 13); |
1226 |
|
tmpi32 >>= 11; |
1227 |
|
ic->arg[0] = (int32_t)tmpi32 + (addr & 0xffc); |
1228 |
|
/* rd contains the annul bit concatenated with 4 bits |
1229 |
|
of condition code. cc=0 for icc, 2 for xcc: */ |
1230 |
|
/* TODO: samepage */ |
1231 |
|
switch (rd + (cc << 5)) { |
1232 |
|
case 0x01: ic->f = instr(be); break; |
1233 |
|
case 0x02: ic->f = instr(ble); break; |
1234 |
|
case 0x03: ic->f = instr(bl); break; |
1235 |
|
case 0x08: ic->f = instr(ba); break; |
1236 |
|
case 0x09: ic->f = instr(bne); break; |
1237 |
|
case 0x0a: ic->f = instr(bg); break; |
1238 |
|
case 0x0b: ic->f = instr(bge); break; |
1239 |
|
case 0x19: ic->f = instr(bne_a); break; |
1240 |
|
case 0x41: ic->f = instr(be_xcc); break; |
1241 |
|
case 0x42: ic->f = instr(ble_xcc);break; |
1242 |
|
case 0x43: ic->f = instr(bl_xcc); break; |
1243 |
|
case 0x48: ic->f = instr(ba); break; |
1244 |
|
case 0x4a: ic->f = instr(bg_xcc); break; |
1245 |
|
case 0x4b: ic->f = instr(bge_xcc);break; |
1246 |
|
default:fatal("Unimplemented branch, 0x%x\n", |
1247 |
|
rd + (cc<<5)); |
1248 |
|
goto bad; |
1249 |
|
} |
1250 |
|
break; |
1251 |
|
|
1252 |
case 2: /* branch (32-bit integer comparison) */ |
case 2: /* branch (32-bit integer comparison) */ |
1253 |
tmpi32 = (iword << 10); |
tmpi32 = (iword << 10); |
1254 |
tmpi32 >>= 8; |
tmpi32 >>= 8; |
1257 |
of condition code: */ |
of condition code: */ |
1258 |
/* TODO: samepage */ |
/* TODO: samepage */ |
1259 |
switch (rd) { |
switch (rd) { |
1260 |
case 0x08:/* ba */ |
case 0x01: ic->f = instr(be); break; |
1261 |
ic->f = instr(ba); |
case 0x03: ic->f = instr(bl); break; |
1262 |
break; |
case 0x08: ic->f = instr(ba); break; |
1263 |
default:goto bad; |
case 0x09: ic->f = instr(bne); break; |
1264 |
|
case 0x0b: ic->f = instr(bge); break; |
1265 |
|
default:fatal("Unimplemented branch rd=%i\n", rd); |
1266 |
|
goto bad; |
1267 |
|
} |
1268 |
|
break; |
1269 |
|
|
1270 |
|
case 3: /* branch on register, 64-bit integer comparison */ |
1271 |
|
tmpi32 = ((iword & 0x300000) >> 6) | (iword & 0x3fff); |
1272 |
|
tmpi32 <<= 16; |
1273 |
|
tmpi32 >>= 14; |
1274 |
|
ic->arg[0] = (int32_t)tmpi32 + (addr & 0xffc); |
1275 |
|
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs1]; |
1276 |
|
/* TODO: samepage */ |
1277 |
|
switch (btype) { |
1278 |
|
case 0x05: ic->f = instr(brnz); break; |
1279 |
|
default:fatal("Unimplemented branch 0x%x\n", rd); |
1280 |
|
goto bad; |
1281 |
} |
} |
1282 |
break; |
break; |
1283 |
|
|
1313 |
case 2: /* or */ |
case 2: /* or */ |
1314 |
case 3: /* xor */ |
case 3: /* xor */ |
1315 |
case 4: /* sub */ |
case 4: /* sub */ |
1316 |
|
case 5: /* andn */ |
1317 |
|
case 14:/* udiv */ |
1318 |
|
case 16:/* addcc */ |
1319 |
|
case 17:/* andcc */ |
1320 |
case 20:/* subcc (cmp) */ |
case 20:/* subcc (cmp) */ |
1321 |
case 37:/* sll */ |
case 37:/* sll */ |
1322 |
case 38:/* srl */ |
case 38:/* srl */ |
1323 |
case 39:/* sra */ |
case 39:/* sra */ |
1324 |
|
case 60:/* save */ |
1325 |
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
1326 |
ic->f = NULL; |
ic->f = NULL; |
1327 |
if (use_imm) { |
if (use_imm) { |
1332 |
case 2: ic->f = instr(or_imm); break; |
case 2: ic->f = instr(or_imm); break; |
1333 |
case 3: ic->f = instr(xor_imm); break; |
case 3: ic->f = instr(xor_imm); break; |
1334 |
case 4: ic->f = instr(sub_imm); break; |
case 4: ic->f = instr(sub_imm); break; |
1335 |
|
case 5: ic->f = instr(andn_imm); break; |
1336 |
|
case 14:ic->f = instr(udiv_imm); break; |
1337 |
|
case 16:ic->f = instr(addcc_imm); break; |
1338 |
|
case 17:ic->f = instr(andcc_imm); break; |
1339 |
case 20:ic->f = instr(subcc_imm); break; |
case 20:ic->f = instr(subcc_imm); break; |
1340 |
case 37:if (siconst & 0x1000) { |
case 37:if (siconst & 0x1000) { |
1341 |
ic->f = instr(sllx_imm); |
ic->f = instr(sllx_imm); |
1364 |
ic->arg[1] &= 31; |
ic->arg[1] &= 31; |
1365 |
} |
} |
1366 |
break; |
break; |
1367 |
|
case 60:switch (cpu->cd.sparc.cpu_type.v) { |
1368 |
|
case 9: ic->f = instr(save_v9_imm); |
1369 |
|
break; |
1370 |
|
default:fatal("only for v9 so far\n"); |
1371 |
|
goto bad; |
1372 |
|
} |
1373 |
} |
} |
1374 |
} else { |
} else { |
1375 |
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs2]; |
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs2]; |
1379 |
case 2: ic->f = instr(or); break; |
case 2: ic->f = instr(or); break; |
1380 |
case 3: ic->f = instr(xor); break; |
case 3: ic->f = instr(xor); break; |
1381 |
case 4: ic->f = instr(sub); break; |
case 4: ic->f = instr(sub); break; |
1382 |
|
case 5: ic->f = instr(andn); break; |
1383 |
|
case 14:ic->f = instr(udiv); break; |
1384 |
|
case 16:ic->f = instr(addcc); break; |
1385 |
|
case 17:ic->f = instr(andcc); break; |
1386 |
case 20:ic->f = instr(subcc); break; |
case 20:ic->f = instr(subcc); break; |
1387 |
case 37:if (siconst & 0x1000) { |
case 37:if (siconst & 0x1000) { |
1388 |
ic->f = instr(sllx); |
ic->f = instr(sllx); |
1411 |
} |
} |
1412 |
ic->arg[2] = (size_t)&cpu->cd.sparc.r[rd]; |
ic->arg[2] = (size_t)&cpu->cd.sparc.r[rd]; |
1413 |
if (rd == SPARC_ZEROREG) { |
if (rd == SPARC_ZEROREG) { |
1414 |
/* Opcodes which update the ccr should use |
/* |
1415 |
the scratch register instead of being |
* Some opcodes should write to the scratch |
1416 |
turned into a nop, when the zero register |
* register instead of becoming NOPs, when |
1417 |
is used as the destination: */ |
* rd is the zero register. |
1418 |
|
* |
1419 |
|
* Any opcode which updates the condition |
1420 |
|
* codes, or anything which changes register |
1421 |
|
* windows. |
1422 |
|
*/ |
1423 |
switch (op2) { |
switch (op2) { |
1424 |
|
case 16:/* addcc */ |
1425 |
|
case 17:/* andcc */ |
1426 |
case 20:/* subcc */ |
case 20:/* subcc */ |
1427 |
|
case 60:/* save */ |
1428 |
ic->arg[2] = (size_t) |
ic->arg[2] = (size_t) |
1429 |
&cpu->cd.sparc.scratch; |
&cpu->cd.sparc.scratch; |
1430 |
break; |
break; |
1446 |
} |
} |
1447 |
break; |
break; |
1448 |
|
|
1449 |
|
case 42:/* rdpr on sparcv9 */ |
1450 |
|
if (cpu->is_32bit) { |
1451 |
|
fatal("opcode 2,42 not yet implemented" |
1452 |
|
" for 32-bit cpus\n"); |
1453 |
|
goto bad; |
1454 |
|
} |
1455 |
|
ic->arg[2] = (size_t)&cpu->cd.sparc.r[rd]; |
1456 |
|
if (rd == SPARC_ZEROREG) |
1457 |
|
ic->f = instr(nop); |
1458 |
|
switch (rs1) { |
1459 |
|
case 5: ic->f = instr(rdpr_tba); break; |
1460 |
|
case 31: ic->f = instr(rdpr_ver); break; |
1461 |
|
default:fatal("Unimplemented rs1=%i\n", rs1); |
1462 |
|
goto bad; |
1463 |
|
} |
1464 |
|
break; |
1465 |
|
|
1466 |
case 48:/* wr (Note: works as xor) */ |
case 48:/* wr (Note: works as xor) */ |
1467 |
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
1468 |
if (use_imm) { |
if (use_imm) { |
1547 |
} |
} |
1548 |
break; |
break; |
1549 |
|
|
1550 |
|
case 57:/* return */ |
1551 |
|
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
1552 |
|
|
1553 |
|
if (use_imm) { |
1554 |
|
ic->arg[1] = siconst; |
1555 |
|
ic->f = instr(return_imm); |
1556 |
|
} else { |
1557 |
|
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs2]; |
1558 |
|
ic->f = instr(return_reg); |
1559 |
|
} |
1560 |
|
|
1561 |
|
/* special trace case: */ |
1562 |
|
if (cpu->machine->show_trace_tree) { |
1563 |
|
if (use_imm) |
1564 |
|
ic->f = instr(return_imm_trace); |
1565 |
|
else |
1566 |
|
ic->f = instr(return_reg_trace); |
1567 |
|
} |
1568 |
|
break; |
1569 |
|
|
1570 |
|
default:fatal("TODO: unimplemented op2=%i for main " |
1571 |
|
"opcode %i\n", op2, main_opcode); |
1572 |
|
goto bad; |
1573 |
|
} |
1574 |
|
break; |
1575 |
|
|
1576 |
|
case 3: switch (op2) { |
1577 |
|
|
1578 |
|
case 0:/* lduw */ |
1579 |
|
case 1:/* ldub */ |
1580 |
|
case 2:/* lduh */ |
1581 |
|
case 4:/* st(w) */ |
1582 |
|
case 5:/* stb */ |
1583 |
|
case 6:/* sth */ |
1584 |
|
case 8:/* ldsw */ |
1585 |
|
case 9:/* ldsb */ |
1586 |
|
case 10:/* ldsh */ |
1587 |
|
case 11:/* ldx */ |
1588 |
|
case 14:/* stx */ |
1589 |
|
store = 1; signedness = 0; size = 3; |
1590 |
|
switch (op2) { |
1591 |
|
case 0: /* lduw */ store=0; size=2; break; |
1592 |
|
case 1: /* ldub */ store=0; size=0; break; |
1593 |
|
case 2: /* lduh */ store=0; size=1; break; |
1594 |
|
case 4: /* st */ size = 2; break; |
1595 |
|
case 5: /* stb */ size = 0; break; |
1596 |
|
case 6: /* sth */ size = 1; break; |
1597 |
|
case 8: /* ldsw */ store=0; size=2; signedness=1; |
1598 |
|
break; |
1599 |
|
case 9: /* ldsb */ store=0; size=0; signedness=1; |
1600 |
|
break; |
1601 |
|
case 10: /* ldsh */ store=0; size=1; signedness=1; |
1602 |
|
break; |
1603 |
|
case 11: /* ldx */ store=0; break; |
1604 |
|
case 14: /* stx */ break; |
1605 |
|
} |
1606 |
|
ic->f = |
1607 |
|
#ifdef MODE32 |
1608 |
|
sparc32_loadstore |
1609 |
|
#else |
1610 |
|
sparc_loadstore |
1611 |
|
#endif |
1612 |
|
[ use_imm*16 + store*8 + size*2 + signedness ]; |
1613 |
|
|
1614 |
|
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rd]; |
1615 |
|
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs1]; |
1616 |
|
if (use_imm) |
1617 |
|
ic->arg[2] = siconst; |
1618 |
|
else |
1619 |
|
ic->arg[2] = (size_t)&cpu->cd.sparc.r[rs2]; |
1620 |
|
|
1621 |
|
if (!store && rd == SPARC_ZEROREG) |
1622 |
|
ic->arg[0] = (size_t)&cpu->cd.sparc.scratch; |
1623 |
|
|
1624 |
|
break; |
1625 |
|
|
1626 |
default:fatal("TODO: unimplemented op2=%i for main " |
default:fatal("TODO: unimplemented op2=%i for main " |
1627 |
"opcode %i\n", op2, main_opcode); |
"opcode %i\n", op2, main_opcode); |
1628 |
goto bad; |
goto bad; |
1629 |
} |
} |
1630 |
break; |
break; |
1631 |
|
|
|
default:fatal("TODO: unimplemented main opcode %i\n", main_opcode); |
|
|
goto bad; |
|
1632 |
} |
} |
1633 |
|
|
1634 |
|
|