25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_sparc_instr.c,v 1.26 2006/12/30 13:30:55 debug Exp $ |
* $Id: cpu_sparc_instr.c,v 1.27 2007/03/16 15:43:58 debug Exp $ |
29 |
* |
* |
30 |
* SPARC instructions. |
* SPARC instructions. |
31 |
* |
* |
1020 |
|
|
1021 |
|
|
1022 |
/* |
/* |
1023 |
|
* flushw: Flush Register Windows |
1024 |
|
*/ |
1025 |
|
X(flushw) |
1026 |
|
{ |
1027 |
|
/* flushw acts as a nop, if cansave = nwindows - 2: */ |
1028 |
|
if (cpu->cd.sparc.cansave == cpu->cd.sparc.cpu_type.nwindows - 2) |
1029 |
|
return; |
1030 |
|
|
1031 |
|
/* TODO */ |
1032 |
|
fatal("flushw: TODO: cansave = %i\n", cpu->cd.sparc.cansave); |
1033 |
|
exit(1); |
1034 |
|
} |
1035 |
|
|
1036 |
|
|
1037 |
|
/* |
1038 |
* rd: Read special register |
* rd: Read special register |
1039 |
* |
* |
1040 |
* arg[2] = ptr to rd |
* arg[2] = ptr to rd |
1092 |
{ |
{ |
1093 |
sparc_update_pstate(cpu, reg(ic->arg[0]) ^ (int32_t)ic->arg[1]); |
sparc_update_pstate(cpu, reg(ic->arg[0]) ^ (int32_t)ic->arg[1]); |
1094 |
} |
} |
1095 |
|
X(wrpr_cleanwin) |
1096 |
|
{ |
1097 |
|
cpu->cd.sparc.cleanwin = (uint32_t) (reg(ic->arg[0]) ^ reg(ic->arg[1])); |
1098 |
|
} |
1099 |
|
X(wrpr_cleanwin_imm) |
1100 |
|
{ |
1101 |
|
cpu->cd.sparc.cleanwin = |
1102 |
|
(uint32_t) (reg(ic->arg[0]) ^ (int32_t)ic->arg[1]); |
1103 |
|
} |
1104 |
|
|
1105 |
|
|
1106 |
/*****************************************************************************/ |
/*****************************************************************************/ |
1487 |
} |
} |
1488 |
break; |
break; |
1489 |
|
|
1490 |
|
case 43:if (iword == 0x81580000) { |
1491 |
|
ic->f = instr(flushw); |
1492 |
|
} else { |
1493 |
|
fatal("Unimplemented iword=0x%08"PRIx32"\n", |
1494 |
|
iword); |
1495 |
|
goto bad; |
1496 |
|
} |
1497 |
|
break; |
1498 |
|
|
1499 |
case 48:/* wr (Note: works as xor) */ |
case 48:/* wr (Note: works as xor) */ |
1500 |
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
ic->arg[0] = (size_t)&cpu->cd.sparc.r[rs1]; |
1501 |
if (use_imm) { |
if (use_imm) { |
1531 |
case 4: ic->f = instr(wrpr_tick_imm); break; |
case 4: ic->f = instr(wrpr_tick_imm); break; |
1532 |
case 6: ic->f = instr(wrpr_pstate_imm); break; |
case 6: ic->f = instr(wrpr_pstate_imm); break; |
1533 |
case 8: ic->f = instr(wrpr_pil_imm); break; |
case 8: ic->f = instr(wrpr_pil_imm); break; |
1534 |
|
case 12:ic->f = instr(wrpr_cleanwin_imm);break; |
1535 |
} |
} |
1536 |
} else { |
} else { |
1537 |
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs2]; |
ic->arg[1] = (size_t)&cpu->cd.sparc.r[rs2]; |
1539 |
case 4: ic->f = instr(wrpr_tick); break; |
case 4: ic->f = instr(wrpr_tick); break; |
1540 |
case 6: ic->f = instr(wrpr_pstate); break; |
case 6: ic->f = instr(wrpr_pstate); break; |
1541 |
case 8: ic->f = instr(wrpr_pil); break; |
case 8: ic->f = instr(wrpr_pil); break; |
1542 |
|
case 12:ic->f = instr(wrpr_cleanwin); break; |
1543 |
} |
} |
1544 |
} |
} |
1545 |
if (ic->f == NULL) { |
if (ic->f == NULL) { |