--- trunk/src/cpus/cpu_sparc.c 2007/10/08 16:19:28 21 +++ trunk/src/cpus/cpu_sparc.c 2007/10/08 16:19:37 22 @@ -25,7 +25,7 @@ * SUCH DAMAGE. * * - * $Id: cpu_sparc.c,v 1.4 2005/11/13 00:14:07 debug Exp $ + * $Id: cpu_sparc.c,v 1.11 2005/12/11 21:34:43 debug Exp $ * * SPARC CPU emulation. */ @@ -41,11 +41,19 @@ #include "misc.h" #include "symbol.h" + #define DYNTRANS_DUALMODE_32 -/* #define DYNTRANS_32 */ #include "tmp_sparc_head.c" +static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES; +static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] = + SPARC_REGBRANCH_NAMES; +static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES; +static char *sparc_alu_names[N_ALU_INSTR_TYPES] = SPARC_ALU_NAMES; +static char *sparc_loadstore_names[N_LOADSTORE_TYPES] = SPARC_LOADSTORE_NAMES; + + /* * sparc_cpu_new(): * @@ -57,22 +65,64 @@ int sparc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, int cpu_id, char *cpu_type_name) { - if (strcasecmp(cpu_type_name, "SPARCv9") != 0) + int any_cache = 0; + int i = 0; + struct sparc_cpu_type_def cpu_type_defs[] = SPARC_CPU_TYPE_DEFS; + + /* Scan the cpu_type_defs list for this cpu type: */ + while (cpu_type_defs[i].name != NULL) { + if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) { + break; + } + i++; + } + if (cpu_type_defs[i].name == NULL) return 0; cpu->memory_rw = sparc_memory_rw; - cpu->update_translation_table = sparc_update_translation_table; - cpu->invalidate_translation_caches = - sparc_invalidate_translation_caches; - cpu->invalidate_code_translation = - sparc_invalidate_code_translation; - cpu->byte_order = EMUL_BIG_ENDIAN; - cpu->is_32bit = 0; + cpu->cd.sparc.cpu_type = cpu_type_defs[i]; + cpu->name = cpu->cd.sparc.cpu_type.name; + cpu->byte_order = EMUL_BIG_ENDIAN; + cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0; + + if (cpu->is_32bit) { + cpu->update_translation_table = + sparc32_update_translation_table; + cpu->invalidate_translation_caches = + sparc32_invalidate_translation_caches; + cpu->invalidate_code_translation = + sparc32_invalidate_code_translation; + } else { + cpu->update_translation_table = sparc_update_translation_table; + cpu->invalidate_translation_caches = + sparc_invalidate_translation_caches; + cpu->invalidate_code_translation = + sparc_invalidate_code_translation; + } /* Only show name and caches etc for CPU nr 0 (in SMP machines): */ if (cpu_id == 0) { debug("%s", cpu->name); + + if (cpu->cd.sparc.cpu_type.icache_shift != 0) + any_cache = 1; + if (cpu->cd.sparc.cpu_type.dcache_shift != 0) + any_cache = 1; + if (cpu->cd.sparc.cpu_type.l2cache_shift != 0) + any_cache = 1; + + if (any_cache) { + debug(" (I+D = %i+%i KB", (int) + (1 << (cpu->cd.sparc.cpu_type.icache_shift-10)), + (int)(1<<(cpu->cd.sparc.cpu_type.dcache_shift-10))); + if (cpu->cd.sparc.cpu_type.l2cache_shift != 0) { + debug(", L2 = %i KB", + (int)(1 << (cpu->cd.sparc.cpu_type. + l2cache_shift-10))); + } + debug(")"); + } } return 1; @@ -86,8 +136,18 @@ */ void sparc_cpu_list_available_types(void) { - debug("SPARCv9\n"); - /* TODO */ + int i, j; + struct sparc_cpu_type_def tdefs[] = SPARC_CPU_TYPE_DEFS; + + i = 0; + while (tdefs[i].name != NULL) { + debug("%s", tdefs[i].name); + for (j=10 - strlen(tdefs[i].name); j>0; j--) + debug(" "); + i++; + if ((i % 6) == 0 || tdefs[i].name == NULL) + debug("\n"); + } } @@ -96,8 +156,7 @@ */ void sparc_cpu_dumpinfo(struct cpu *cpu) { - debug("\n"); - /* TODO */ + debug(", %i-bit\n", cpu->cd.sparc.cpu_type.bits); } @@ -113,22 +172,56 @@ { char *symbol; uint64_t offset; - int x = cpu->cpu_id; - int bits32 = 0; + int i, x = cpu->cpu_id; + int bits32 = cpu->is_32bit; if (gprs) { /* Special registers (pc, ...) first: */ symbol = get_symbol_name(&cpu->machine->symbol_context, cpu->pc, &offset); - debug("cpu%i: pc = 0x", x); + debug("cpu%i: pc = 0x", x); if (bits32) debug("%08x", (int)cpu->pc); else debug("%016llx", (long long)cpu->pc); debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); - /* TODO */ + if (bits32) { + for (i=0; icd.sparc.r[i]); + if ((i & 3) < 3) + debug(" "); + else + debug("\n"); + } + } else { + for (i=0; i> 1) & 15) | ((i&1) << 4); + if ((i & 1) == 0) + debug("cpu%i: ", x); + /* Skip the zero register: */ + if (r==0) { + debug(" "); + continue; + } + debug("%s = ", sparc_regnames[r]); + debug("0x%016llx", (long long) + cpu->cd.sparc.r[r]); + if ((i & 1) < 1) + debug(" "); + else + debug("\n"); + } + } } } @@ -191,10 +284,11 @@ int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, int running, uint64_t dumpaddr, int bintrans) { - uint64_t offset; + uint64_t offset, tmp; uint32_t iword; - int hi6; - char *symbol; + int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0; + int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p; + char *symbol, *mnem; if (running) dumpaddr = cpu->pc; @@ -207,26 +301,218 @@ if (cpu->machine->ncpus > 1 && running) debug("cpu%i: ", cpu->cpu_id); -/* if (cpu->cd.sparc.bits == 32) + if (cpu->is_32bit) debug("%08x", (int)dumpaddr); else -*/ debug("%016llx", (long long)dumpaddr); + debug("%016llx", (long long)dumpaddr); - iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) - + instr[3]; + iword = *(uint32_t *)&instr[0]; + iword = BE32_TO_HOST(iword); debug(": %08x\t", iword); /* * Decode the instruction: + * + * http://www.cs.unm.edu/~maccabe/classes/341/labman/node9.html is a + * good quick description of SPARC instruction encoding. */ - hi6 = iword >> 26; - - switch (hi6) { - default: - /* TODO */ - debug("unimplemented hi6 = 0x%02x", hi6); + hi2 = iword >> 30; + rd = (iword >> 25) & 31; + btype = rd & (N_SPARC_BRANCH_TYPES - 1); + rs1 = (iword >> 14) & 31; + asi = (iword >> 5) & 0xff; + rs2 = iword & 31; + siconst = (int16_t)((iword & 0x1fff) << 3) >> 3; + op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f); + cc = (iword >> 20) & 3; + p = (iword >> 19) & 1; + + switch (hi2) { + + case 0: switch (op2) { + + case 0: debug("illtrap\t0x%x", iword & 0x3fffff); + break; + + case 1: + case 2: + case 3: if (op2 == 3) + debug("%s", sparc_regbranch_names[btype & 7]); + else + debug("%s", sparc_branch_names[btype]); + if (rd & 16) + debug(",a"); + tmps = iword; + switch (op2) { + case 1: tmps <<= 13; + tmps >>= 11; + if (!p) + debug(",pn"); + debug("\t%%%s,", cc==0 ? "icc" : + (cc==2 ? "xcc" : "UNKNOWN")); + break; + case 2: tmps <<= 10; + tmps >>= 8; + debug("\t"); + break; + case 3: if (btype & 8) + debug("(INVALID)"); + if (!p) + debug(",pn"); + debug("\t%%%s,", sparc_regnames[rs1]); + tmps = ((iword & 0x300000) >> 6) + | (iword & 0x3fff); + tmps <<= 16; + tmps >>= 14; + break; + } + tmp = (int64_t)(int32_t)tmps; + tmp += dumpaddr; + debug("0x%llx", (long long)tmp); + symbol = get_symbol_name(&cpu->machine-> + symbol_context, tmp, &offset); + if (symbol != NULL) + debug(" \t<%s>", symbol); + break; + + case 4: if (rd == 0) { + debug("nop"); + break; + } + debug("sethi\t%%hi(0x%x),", (iword & 0x3fffff) << 10); + debug("%%%s", sparc_regnames[rd]); + break; + + default:debug("UNIMPLEMENTED hi2=%i, op2=0x%x", hi2, op2); + } + break; + + case 1: tmp = (int32_t)iword << 2; + tmp += dumpaddr; + debug("call\t0x%llx", (long long)tmp); + symbol = get_symbol_name(&cpu->machine->symbol_context, + tmp, &offset); + if (symbol != NULL) + debug(" \t<%s>", symbol); + break; + + case 2: mnem = sparc_alu_names[op2]; + switch (op2) { + case 0: /* add */ + if (rd == rs1 && (iword & 0x3fff) == 0x2001) { + mnem = "inc"; + no_rs1 = no_rs2 = 1; + } + break; + case 2: /* or */ + if (rs1 == 0) { + mnem = "mov"; + no_rs1 = 1; + } + break; + case 4: /* sub */ + if (rd == rs1 && (iword & 0x3fff) == 0x2001) { + mnem = "dec"; + no_rs1 = no_rs2 = 1; + } + break; + case 20:/* subcc */ + if (rd == 0) { + mnem = "cmp"; + no_rd = 1; + } + break; + case 37:/* sll */ + case 38:/* srl */ + case 39:/* sra */ + if (siconst & 0x1000) { + siconst &= 0x3f; + shift_x = 1; + } else + siconst &= 0x1f; + break; + case 43:/* ? */ + if (iword == 0x81580000) { + mnem = "flushw"; + no_rs1 = no_rs2 = no_rd = 1; + } + break; + case 49:/* ? */ + if (iword == 0x83880000) { + mnem = "restored"; + no_rs1 = no_rs2 = no_rd = 1; + } + break; + case 56:/* jmpl */ + jmpl = 1; + if (iword == 0x81c7e008) { + mnem = "ret"; + no_rs1 = no_rs2 = no_rd = 1; + } + if (iword == 0x81c3e008) { + mnem = "retl"; + no_rs1 = no_rs2 = no_rd = 1; + } + break; + case 61:/* restore */ + if (iword == 0x81e80000) + no_rs1 = no_rs2 = no_rd = 1; + break; + case 62:if (iword == 0x83f00000) { + mnem = "retry"; + no_rs1 = no_rs2 = no_rd = 1; + } + break; + } + debug("%s", mnem); + if (shift_x) + debug("x"); + debug("\t"); + if (!no_rs1) + debug("%%%s", sparc_regnames[rs1]); + if (!no_rs1 && !no_rs2) { + if (jmpl) + debug("+"); + else + debug(","); + } + if (!no_rs2) { + if ((iword >> 13) & 1) { + if (siconst >= -9 && siconst <= 9) + debug("%i", siconst); + else + debug("0x%x", siconst); + } else { + debug("%%%s", sparc_regnames[rs2]); + } + } + if ((!no_rs1 || !no_rs2) && !no_rd) + debug(","); + if (!no_rd) + debug("%%%s", sparc_regnames[rd]); + break; + + case 3: debug("%s\t", sparc_loadstore_names[op2]); + if (op2 & 4) + debug("%%%s,", sparc_regnames[rd]); + debug("[%%%s", sparc_regnames[rs1]); + if ((iword >> 13) & 1) { + if (siconst > 0) + debug("+"); + if (siconst != 0) + debug("%i", siconst); + } else { + if (rs2 != 0) + debug("+%%%s", sparc_regnames[rs2]); + } + debug("]"); + if (asi != 0) + debug("(%i)", asi); + if (!(op2 & 4)) + debug(",%%%s", sparc_regnames[rd]); + break; } debug("\n");