/[gxemul]/trunk/src/cpus/cpu_sparc.c
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Contents of /trunk/src/cpus/cpu_sparc.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 19429 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_sparc.c,v 1.39 2006/12/30 13:30:55 debug Exp $
29 *
30 * SPARC CPU emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "cpu.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42 #include "settings.h"
43 #include "symbol.h"
44
45
46 #define DYNTRANS_DUALMODE_32
47 #define DYNTRANS_DELAYSLOT
48 #include "tmp_sparc_head.c"
49
50
51 static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES;
52 static char *sparc_pregnames[N_SPARC_PREG] = SPARC_PREG_NAMES;
53 static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] =
54 SPARC_REGBRANCH_NAMES;
55 static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES;
56 static char *sparc_alu_names[N_ALU_INSTR_TYPES] = SPARC_ALU_NAMES;
57 static char *sparc_loadstore_names[N_LOADSTORE_TYPES] = SPARC_LOADSTORE_NAMES;
58
59
60 /*
61 * sparc_cpu_new():
62 *
63 * Create a new SPARC cpu object.
64 *
65 * Returns 1 on success, 0 if there was no matching SPARC processor with
66 * this cpu_type_name.
67 */
68 int sparc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
69 int cpu_id, char *cpu_type_name)
70 {
71 int any_cache = 0;
72 int i = 0;
73 struct sparc_cpu_type_def cpu_type_defs[] = SPARC_CPU_TYPE_DEFS;
74
75 /* Scan the cpu_type_defs list for this cpu type: */
76 while (cpu_type_defs[i].name != NULL) {
77 if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
78 break;
79 }
80 i++;
81 }
82 if (cpu_type_defs[i].name == NULL)
83 return 0;
84
85 cpu->memory_rw = sparc_memory_rw;
86
87 cpu->cd.sparc.cpu_type = cpu_type_defs[i];
88 cpu->name = cpu->cd.sparc.cpu_type.name;
89 cpu->byte_order = EMUL_BIG_ENDIAN;
90 cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0;
91
92 cpu->instruction_has_delayslot = sparc_cpu_instruction_has_delayslot;
93
94 /* TODO: Separate this into 64-bit vs 32-bit? */
95 cpu->translate_v2p = sparc_translate_v2p;
96
97 if (cpu->is_32bit) {
98 cpu->run_instr = sparc32_run_instr;
99 cpu->update_translation_table =
100 sparc32_update_translation_table;
101 cpu->invalidate_translation_caches =
102 sparc32_invalidate_translation_caches;
103 cpu->invalidate_code_translation =
104 sparc32_invalidate_code_translation;
105 } else {
106 cpu->run_instr = sparc_run_instr;
107 cpu->update_translation_table = sparc_update_translation_table;
108 cpu->invalidate_translation_caches =
109 sparc_invalidate_translation_caches;
110 cpu->invalidate_code_translation =
111 sparc_invalidate_code_translation;
112 }
113
114 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
115 if (cpu_id == 0) {
116 debug("%s", cpu->name);
117
118 if (cpu->cd.sparc.cpu_type.icache_shift != 0)
119 any_cache = 1;
120 if (cpu->cd.sparc.cpu_type.dcache_shift != 0)
121 any_cache = 1;
122 if (cpu->cd.sparc.cpu_type.l2cache_shift != 0)
123 any_cache = 1;
124
125 if (any_cache) {
126 debug(" (I+D = %i+%i KB", (int)
127 (1 << (cpu->cd.sparc.cpu_type.icache_shift-10)),
128 (int)(1<<(cpu->cd.sparc.cpu_type.dcache_shift-10)));
129 if (cpu->cd.sparc.cpu_type.l2cache_shift != 0) {
130 debug(", L2 = %i KB",
131 (int)(1 << (cpu->cd.sparc.cpu_type.
132 l2cache_shift-10)));
133 }
134 debug(")");
135 }
136 }
137
138 /* After a reset, the Tick register is not readable by user code: */
139 cpu->cd.sparc.tick |= SPARC_TICK_NPT;
140
141 /* Insert number of Windows and Trap levels into the version reg.: */
142 cpu->cd.sparc.ver |= MAXWIN | (MAXTL << SPARC_VER_MAXTL_SHIFT);
143
144 /* Misc. initial settings suitable for userland emulation: */
145 cpu->cd.sparc.cansave = cpu->cd.sparc.cpu_type.nwindows - 1;
146 cpu->cd.sparc.cleanwin = cpu->cd.sparc.cpu_type.nwindows / 2;
147
148 if (cpu->cd.sparc.cpu_type.nwindows >= MAXWIN) {
149 fatal("Fatal internal error: nwindows = %1 is more than %i\n",
150 cpu->cd.sparc.cpu_type.nwindows, MAXWIN);
151 exit(1);
152 }
153
154 CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
155 CPU_SETTINGS_ADD_REGISTER64("y", cpu->cd.sparc.y);
156 CPU_SETTINGS_ADD_REGISTER64("pstate", cpu->cd.sparc.pstate);
157 for (i=0; i<N_SPARC_REG; i++)
158 CPU_SETTINGS_ADD_REGISTER64(sparc_regnames[i],
159 cpu->cd.sparc.r[i]);
160 /* TODO: Handler for writes to the zero register! */
161
162 return 1;
163 }
164
165
166 /*
167 * sparc_cpu_list_available_types():
168 *
169 * Print a list of available SPARC CPU types.
170 */
171 void sparc_cpu_list_available_types(void)
172 {
173 int i, j;
174 struct sparc_cpu_type_def tdefs[] = SPARC_CPU_TYPE_DEFS;
175
176 i = 0;
177 while (tdefs[i].name != NULL) {
178 debug("%s", tdefs[i].name);
179 for (j=16 - strlen(tdefs[i].name); j>0; j--)
180 debug(" ");
181 i++;
182 if ((i % 4) == 0 || tdefs[i].name == NULL)
183 debug("\n");
184 }
185 }
186
187
188 /*
189 * sparc_cpu_dumpinfo():
190 */
191 void sparc_cpu_dumpinfo(struct cpu *cpu)
192 {
193 debug(", %i-bit\n", cpu->cd.sparc.cpu_type.bits);
194 }
195
196
197 /*
198 * sparc_cpu_register_dump():
199 *
200 * Dump cpu registers in a relatively readable format.
201 *
202 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
203 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
204 */
205 void sparc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
206 {
207 char *symbol;
208 uint64_t offset;
209 int i, x = cpu->cpu_id;
210 int bits32 = cpu->is_32bit;
211
212 if (gprs) {
213 /* Special registers (pc, ...) first: */
214 symbol = get_symbol_name(&cpu->machine->symbol_context,
215 cpu->pc, &offset);
216
217 debug("cpu%i: pc = 0x", x);
218 if (bits32)
219 debug("%08"PRIx32, (uint32_t) cpu->pc);
220 else
221 debug("%016"PRIx64, (uint64_t) cpu->pc);
222 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
223
224 debug("cpu%i: y = 0x%08"PRIx32" ",
225 x, (uint32_t)cpu->cd.sparc.y);
226 debug("icc = ");
227 debug(cpu->cd.sparc.ccr & SPARC_CCR_N? "N" : "n");
228 debug(cpu->cd.sparc.ccr & SPARC_CCR_Z? "Z" : "z");
229 debug(cpu->cd.sparc.ccr & SPARC_CCR_V? "V" : "v");
230 debug(cpu->cd.sparc.ccr & SPARC_CCR_C? "C" : "c");
231 if (!bits32) {
232 debug(" xcc = ");
233 debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT)
234 & SPARC_CCR_N? "N" : "n");
235 debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT)
236 & SPARC_CCR_Z? "Z" : "z");
237 debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT)
238 & SPARC_CCR_V? "V" : "v");
239 debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT)
240 & SPARC_CCR_C? "C" : "c");
241 }
242 debug("\n");
243
244 if (bits32)
245 debug("cpu%i: psr = 0x%08"PRIx32"\n",
246 x, (uint32_t) cpu->cd.sparc.psr);
247 else
248 debug("cpu%i: pstate = 0x%016"PRIx64"\n",
249 x, (uint64_t) cpu->cd.sparc.pstate);
250
251 if (bits32) {
252 for (i=0; i<N_SPARC_REG; i++) {
253 if ((i & 3) == 0)
254 debug("cpu%i: ", x);
255 /* Skip the zero register: */
256 if (i == SPARC_ZEROREG) {
257 debug(" ");
258 continue;
259 }
260 debug("%s=", sparc_regnames[i]);
261 debug("0x%08x", (int) cpu->cd.sparc.r[i]);
262 if ((i & 3) < 3)
263 debug(" ");
264 else
265 debug("\n");
266 }
267 } else {
268 for (i=0; i<N_SPARC_REG; i++) {
269 int r = ((i >> 1) & 15) | ((i&1) << 4);
270 if ((i & 1) == 0)
271 debug("cpu%i: ", x);
272
273 /* Skip the zero register: */
274 if (i == SPARC_ZEROREG) {
275 debug(" ");
276 continue;
277 }
278
279 debug("%s = ", sparc_regnames[r]);
280 debug("0x%016"PRIx64, (uint64_t)
281 cpu->cd.sparc.r[r]);
282
283 if ((i & 1) < 1)
284 debug(" ");
285 else
286 debug("\n");
287 }
288 }
289 }
290 }
291
292
293 /*
294 * sparc_cpu_tlbdump():
295 *
296 * Called from the debugger to dump the TLB in a readable format.
297 * x is the cpu number to dump, or -1 to dump all CPUs.
298 *
299 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
300 * just dumped.
301 */
302 void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag)
303 {
304 }
305
306
307 static void add_response_word(struct cpu *cpu, char *r, uint64_t value,
308 size_t maxlen, int len)
309 {
310 char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64;
311 if (len == 4)
312 value &= 0xffffffffULL;
313 if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
314 if (len == 4) {
315 value = ((value & 0xff) << 24) +
316 ((value & 0xff00) << 8) +
317 ((value & 0xff0000) >> 8) +
318 ((value & 0xff000000) >> 24);
319 } else {
320 value = ((value & 0xff) << 56) +
321 ((value & 0xff00) << 40) +
322 ((value & 0xff0000) << 24) +
323 ((value & 0xff000000ULL) << 8) +
324 ((value & 0xff00000000ULL) >> 8) +
325 ((value & 0xff0000000000ULL) >> 24) +
326 ((value & 0xff000000000000ULL) >> 40) +
327 ((value & 0xff00000000000000ULL) >> 56);
328 }
329 }
330 snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value);
331 }
332
333
334 /*
335 * sparc_cpu_gdb_stub():
336 *
337 * Execute a "remote GDB" command. Returns a newly allocated response string
338 * on success, NULL on failure.
339 */
340 char *sparc_cpu_gdb_stub(struct cpu *cpu, char *cmd)
341 {
342 if (strcmp(cmd, "g") == 0) {
343 int i;
344 char *r;
345 size_t wlen = cpu->is_32bit?
346 sizeof(uint32_t) : sizeof(uint64_t);
347 size_t len = 1 + 76 * wlen;
348 r = malloc(len);
349 if (r == NULL) {
350 fprintf(stderr, "out of memory\n");
351 exit(1);
352 }
353 r[0] = '\0';
354 /* TODO */
355 for (i=0; i<128; i++)
356 add_response_word(cpu, r, i, len, wlen);
357 return r;
358 }
359
360 if (cmd[0] == 'p') {
361 int regnr = strtol(cmd + 1, NULL, 16);
362 size_t wlen = sizeof(uint32_t);
363 /* TODO: cpu->is_32bit? sizeof(uint32_t) : sizeof(uint64_t); */
364 size_t len = 2 * wlen + 1;
365 char *r = malloc(len);
366 r[0] = '\0';
367 if (regnr >= 0 && regnr < N_SPARC_REG) {
368 add_response_word(cpu, r,
369 cpu->cd.sparc.r[regnr], len, wlen);
370 } else if (regnr == 0x44) {
371 add_response_word(cpu, r, cpu->pc, len, wlen);
372 /* TODO:
373 20..3f = f0..f31
374 40 = y
375 41 = psr
376 42 = wim
377 43 = tbr
378 45 = npc
379 46 = fsr
380 47 = csr
381 */
382 } else {
383 /* Unimplemented: */
384 add_response_word(cpu, r, 0xcc000 + regnr, len, wlen);
385 }
386 return r;
387 }
388
389 fatal("sparc_cpu_gdb_stub(): TODO\n");
390 return NULL;
391 }
392
393
394 /*
395 * sparc_cpu_interrupt():
396 */
397 int sparc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
398 {
399 fatal("sparc_cpu_interrupt(): TODO\n");
400 return 0;
401 }
402
403
404 /*
405 * sparc_cpu_interrupt_ack():
406 */
407 int sparc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
408 {
409 /* fatal("sparc_cpu_interrupt_ack(): TODO\n"); */
410 return 0;
411 }
412
413
414 /*
415 * sparc_cpu_instruction_has_delayslot():
416 *
417 * Return 1 if an opcode is a branch, 0 otherwise.
418 */
419 int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
420 {
421 uint32_t iword = *((uint32_t *)&ib[0]);
422 int hi2, op2;
423
424 iword = BE32_TO_HOST(iword);
425
426 hi2 = iword >> 30;
427 op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f);
428
429 switch (hi2) {
430 case 0: /* conditional branch */
431 switch (op2) {
432 case 1:
433 case 2:
434 case 3: return 1;
435 }
436 break;
437 case 1: /* call */
438 return 1;
439 case 2: /* misc alu instructions */
440 switch (op2) {
441 case 56:/* jump and link */
442 return 1;
443 case 57:/* return */
444 return 1;
445 }
446 break;
447 }
448
449 return 0;
450 }
451
452
453 /*
454 * sparc_cpu_disassemble_instr():
455 *
456 * Convert an instruction word into human readable format, for instruction
457 * tracing.
458 *
459 * If running is 1, cpu->pc should be the address of the instruction.
460 *
461 * If running is 0, things that depend on the runtime environment (eg.
462 * register contents) will not be shown, and addr will be used instead of
463 * cpu->pc for relative addresses.
464 */
465 int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
466 int running, uint64_t dumpaddr)
467 {
468 uint64_t offset, tmp;
469 uint32_t iword;
470 int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0;
471 int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p;
472 char *symbol, *mnem, *rd_name, *rs_name;
473
474 if (running)
475 dumpaddr = cpu->pc;
476
477 symbol = get_symbol_name(&cpu->machine->symbol_context,
478 dumpaddr, &offset);
479 if (symbol != NULL && offset==0)
480 debug("<%s>\n", symbol);
481
482 if (cpu->machine->ncpus > 1 && running)
483 debug("cpu%i: ", cpu->cpu_id);
484
485 if (cpu->is_32bit)
486 debug("%08"PRIx32, (uint32_t) dumpaddr);
487 else
488 debug("%016"PRIx64, (uint64_t) dumpaddr);
489
490 iword = *(uint32_t *)&instr[0];
491 iword = BE32_TO_HOST(iword);
492
493 debug(": %08x", iword);
494
495 if (running && cpu->delay_slot)
496 debug(" (d)");
497
498 debug("\t");
499
500
501 /*
502 * Decode the instruction:
503 *
504 * http://www.cs.unm.edu/~maccabe/classes/341/labman/node9.html is a
505 * good quick description of SPARC instruction encoding.
506 */
507
508 hi2 = iword >> 30;
509 rd = (iword >> 25) & 31;
510 btype = rd & (N_SPARC_BRANCH_TYPES - 1);
511 rs1 = (iword >> 14) & 31;
512 asi = (iword >> 5) & 0xff;
513 rs2 = iword & 31;
514 siconst = (int16_t)((iword & 0x1fff) << 3) >> 3;
515 op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f);
516 cc = (iword >> 20) & 3;
517 p = (iword >> 19) & 1;
518
519 switch (hi2) {
520
521 case 0: switch (op2) {
522
523 case 0: debug("illtrap\t0x%x", iword & 0x3fffff);
524 break;
525
526 case 1:
527 case 2:
528 case 3: if (op2 == 3)
529 debug("%s", sparc_regbranch_names[btype & 7]);
530 else
531 debug("%s", sparc_branch_names[btype]);
532 if (rd & 16)
533 debug(",a");
534 tmps = iword;
535 switch (op2) {
536 case 1: tmps <<= 13;
537 tmps >>= 11;
538 if (!p)
539 debug(",pn");
540 debug("\t%%%s,", cc==0 ? "icc" :
541 (cc==2 ? "xcc" : "UNKNOWN"));
542 break;
543 case 2: tmps <<= 10;
544 tmps >>= 8;
545 debug("\t");
546 break;
547 case 3: if (btype & 8)
548 debug("(INVALID)");
549 if (!p)
550 debug(",pn");
551 debug("\t%%%s,", sparc_regnames[rs1]);
552 tmps = ((iword & 0x300000) >> 6)
553 | (iword & 0x3fff);
554 tmps <<= 16;
555 tmps >>= 14;
556 break;
557 }
558 tmp = (int64_t)(int32_t)tmps;
559 tmp += dumpaddr;
560 debug("0x%"PRIx64, (uint64_t) tmp);
561 symbol = get_symbol_name(&cpu->machine->
562 symbol_context, tmp, &offset);
563 if (symbol != NULL)
564 debug(" \t<%s>", symbol);
565 break;
566
567 case 4: if (rd == 0) {
568 debug("nop");
569 break;
570 }
571 debug("sethi\t%%hi(0x%x),", (iword & 0x3fffff) << 10);
572 debug("%%%s", sparc_regnames[rd]);
573 break;
574
575 default:debug("UNIMPLEMENTED hi2=%i, op2=0x%x", hi2, op2);
576 }
577 break;
578
579 case 1: tmp = (int32_t)iword << 2;
580 tmp += dumpaddr;
581 debug("call\t0x%"PRIx64, (uint64_t) tmp);
582 symbol = get_symbol_name(&cpu->machine->symbol_context,
583 tmp, &offset);
584 if (symbol != NULL)
585 debug(" \t<%s>", symbol);
586 break;
587
588 case 2: mnem = sparc_alu_names[op2];
589 rs_name = sparc_regnames[rs1];
590 rd_name = sparc_regnames[rd];
591 switch (op2) {
592 case 0: /* add */
593 if (rd == rs1 && (iword & 0x3fff) == 0x2001) {
594 mnem = "inc";
595 no_rs1 = no_rs2 = 1;
596 }
597 break;
598 case 2: /* or */
599 if (rs1 == 0) {
600 mnem = "mov";
601 no_rs1 = 1;
602 }
603 break;
604 case 4: /* sub */
605 if (rd == rs1 && (iword & 0x3fff) == 0x2001) {
606 mnem = "dec";
607 no_rs1 = no_rs2 = 1;
608 }
609 break;
610 case 20:/* subcc */
611 if (rd == 0) {
612 mnem = "cmp";
613 no_rd = 1;
614 }
615 break;
616 case 37:/* sll */
617 case 38:/* srl */
618 case 39:/* sra */
619 if (siconst & 0x1000) {
620 siconst &= 0x3f;
621 shift_x = 1;
622 } else
623 siconst &= 0x1f;
624 break;
625 case 40:/* rd on pre-sparcv9, membar etc on sparcv9 */
626 no_rs2 = 1;
627 rs_name = "UNIMPLEMENTED";
628 switch (rs1) {
629 case 0: rs_name = "y"; break;
630 case 2: rs_name = "ccr"; break;
631 case 3: rs_name = "asi"; break;
632 case 4: rs_name = "tick"; break;
633 case 5: rs_name = "pc"; break;
634 case 6: rs_name = "fprs"; break;
635 case 15:/* membar etc. */
636 if ((iword >> 13) & 1) {
637 no_rd = 1;
638 mnem = "membar";
639 rs_name = "#TODO";
640 }
641 break;
642 case 23:rs_name = "tick_cmpr"; break; /* v9 ? */
643 }
644 break;
645 case 41:rs_name = "psr";
646 no_rs2 = 1;
647 break;
648 case 42:/* TODO: something with wim only, on sparc v8? */
649 rs_name = sparc_pregnames[rs1];
650 no_rs2 = 1;
651 break;
652 case 43:/* ? */
653 /* TODO: pre-sparcv9: rd, rs_name = "tbr"; */
654 if (iword == 0x81580000) {
655 mnem = "flushw";
656 no_rs1 = no_rs2 = no_rd = 1;
657 }
658 break;
659 case 48:/* wr* (SPARCv8) */
660 mnem = "wr";
661 if (rs1 == SPARC_ZEROREG)
662 no_rs1 = 1;
663 switch (rd) {
664 case 0: rd_name = "y"; break;
665 case 2: rd_name = "ccr"; break;
666 case 3: rd_name = "asi"; break;
667 case 6: rd_name = "fprs"; break;
668 case 23:rd_name = "tick_cmpr"; break; /* v9 ? */
669 default:rd_name = "UNIMPLEMENTED";
670 }
671 break;
672 case 49:/* ? */
673 if (iword == 0x83880000) {
674 mnem = "restored";
675 no_rs1 = no_rs2 = no_rd = 1;
676 }
677 break;
678 case 50:/* wrpr */
679 rd_name = sparc_pregnames[rd];
680 if (rs1 == SPARC_ZEROREG)
681 no_rs1 = 1;
682 break;
683 case 56:/* jmpl */
684 jmpl = 1;
685 if (iword == 0x81c7e008) {
686 mnem = "ret";
687 no_rs1 = no_rs2 = no_rd = 1;
688 }
689 if (iword == 0x81c3e008) {
690 mnem = "retl";
691 no_rs1 = no_rs2 = no_rd = 1;
692 }
693 break;
694 case 61:/* restore */
695 if (iword == 0x81e80000)
696 no_rs1 = no_rs2 = no_rd = 1;
697 break;
698 case 62:if (iword == 0x83f00000) {
699 mnem = "retry";
700 no_rs1 = no_rs2 = no_rd = 1;
701 }
702 break;
703 }
704 debug("%s", mnem);
705 if (shift_x)
706 debug("x");
707 debug("\t");
708 if (!no_rs1)
709 debug("%%%s", rs_name);
710 if (!no_rs1 && !no_rs2) {
711 if (jmpl)
712 debug("+");
713 else
714 debug(",");
715 }
716 if (!no_rs2) {
717 if ((iword >> 13) & 1) {
718 if (siconst >= -9 && siconst <= 9)
719 debug("%i", siconst);
720 else if (siconst < 0 && (op2 == 0 ||
721 op2 == 4 || op2 == 20 || op2 == 60))
722 debug("-0x%x", -siconst);
723 else
724 debug("0x%x", siconst);
725 } else {
726 debug("%%%s", sparc_regnames[rs2]);
727 }
728 }
729 if ((!no_rs1 || !no_rs2) && !no_rd)
730 debug(",");
731 if (!no_rd)
732 debug("%%%s", rd_name);
733 break;
734
735 case 3: mnem = sparc_loadstore_names[op2];
736 switch (op2) {
737 case 0: /* 'lduw' was called only 'ld' in pre-v9 */
738 if (cpu->cd.sparc.cpu_type.v < 9)
739 mnem = "ld";
740 break;
741 }
742 debug("%s\t", mnem);
743 if (op2 & 4)
744 debug("%%%s,", sparc_regnames[rd]);
745 debug("[%%%s", sparc_regnames[rs1]);
746 if ((iword >> 13) & 1) {
747 if (siconst > 0)
748 debug("+");
749 if (siconst != 0)
750 debug("%i", siconst);
751 } else {
752 if (rs2 != 0)
753 debug("+%%%s", sparc_regnames[rs2]);
754 }
755 debug("]");
756 if ((op2 & 0x30) == 0x10)
757 debug("(%i)", asi);
758 if (!(op2 & 4))
759 debug(",%%%s", sparc_regnames[rd]);
760 break;
761 }
762
763 debug("\n");
764 return sizeof(iword);
765 }
766
767
768 /*
769 * sparc_update_pstate():
770 *
771 * Update the pstate register (64-bit sparcs).
772 */
773 static void sparc_update_pstate(struct cpu *cpu, uint64_t new_pstate)
774 {
775 /* uint64_t old_pstate = cpu->cd.sparc.pstate; */
776
777 /* TODO: Check individual bits. */
778
779 cpu->cd.sparc.pstate = new_pstate;
780 }
781
782
783 #include "tmp_sparc_tail.c"
784
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