1 |
/* |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_sparc.c,v 1.11 2005/12/11 21:34:43 debug Exp $ |
* $Id: cpu_sparc.c,v 1.34 2006/07/16 13:32:26 debug Exp $ |
29 |
* |
* |
30 |
* SPARC CPU emulation. |
* SPARC CPU emulation. |
31 |
*/ |
*/ |
43 |
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44 |
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45 |
#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
46 |
|
#define DYNTRANS_DELAYSLOT |
47 |
#include "tmp_sparc_head.c" |
#include "tmp_sparc_head.c" |
48 |
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|
49 |
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50 |
static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES; |
static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES; |
51 |
|
static char *sparc_pregnames[N_SPARC_PREG] = SPARC_PREG_NAMES; |
52 |
static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] = |
static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] = |
53 |
SPARC_REGBRANCH_NAMES; |
SPARC_REGBRANCH_NAMES; |
54 |
static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES; |
static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES; |
88 |
cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
89 |
cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0; |
90 |
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|
91 |
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cpu->instruction_has_delayslot = sparc_cpu_instruction_has_delayslot; |
92 |
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|
93 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
94 |
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cpu->run_instr = sparc32_run_instr; |
95 |
cpu->update_translation_table = |
cpu->update_translation_table = |
96 |
sparc32_update_translation_table; |
sparc32_update_translation_table; |
97 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
99 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
100 |
sparc32_invalidate_code_translation; |
sparc32_invalidate_code_translation; |
101 |
} else { |
} else { |
102 |
|
cpu->run_instr = sparc_run_instr; |
103 |
cpu->update_translation_table = sparc_update_translation_table; |
cpu->update_translation_table = sparc_update_translation_table; |
104 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
105 |
sparc_invalidate_translation_caches; |
sparc_invalidate_translation_caches; |
131 |
} |
} |
132 |
} |
} |
133 |
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|
134 |
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/* After a reset, the Tick register is not readable by user code: */ |
135 |
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cpu->cd.sparc.tick |= SPARC_TICK_NPT; |
136 |
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|
137 |
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/* Insert number of Windows and Trap levels into the version reg.: */ |
138 |
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cpu->cd.sparc.ver |= MAXWIN | (MAXTL << SPARC_VER_MAXTL_SHIFT); |
139 |
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|
140 |
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/* Misc. initial settings suitable for userland emulation: */ |
141 |
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cpu->cd.sparc.cansave = cpu->cd.sparc.cpu_type.nwindows - 1; |
142 |
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cpu->cd.sparc.cleanwin = cpu->cd.sparc.cpu_type.nwindows / 2; |
143 |
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144 |
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if (cpu->cd.sparc.cpu_type.nwindows >= MAXWIN) { |
145 |
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fatal("Fatal internal error: nwindows = %1 is more than %i\n", |
146 |
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cpu->cd.sparc.cpu_type.nwindows, MAXWIN); |
147 |
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exit(1); |
148 |
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} |
149 |
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150 |
return 1; |
return 1; |
151 |
} |
} |
152 |
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164 |
i = 0; |
i = 0; |
165 |
while (tdefs[i].name != NULL) { |
while (tdefs[i].name != NULL) { |
166 |
debug("%s", tdefs[i].name); |
debug("%s", tdefs[i].name); |
167 |
for (j=10 - strlen(tdefs[i].name); j>0; j--) |
for (j=16 - strlen(tdefs[i].name); j>0; j--) |
168 |
debug(" "); |
debug(" "); |
169 |
i++; |
i++; |
170 |
if ((i % 6) == 0 || tdefs[i].name == NULL) |
if ((i % 4) == 0 || tdefs[i].name == NULL) |
171 |
debug("\n"); |
debug("\n"); |
172 |
} |
} |
173 |
} |
} |
204 |
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|
205 |
debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
206 |
if (bits32) |
if (bits32) |
207 |
debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t) cpu->pc); |
208 |
else |
else |
209 |
debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t) cpu->pc); |
210 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
211 |
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212 |
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debug("cpu%i: y = 0x%08"PRIx32" ", |
213 |
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x, (uint32_t)cpu->cd.sparc.y); |
214 |
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debug("icc = "); |
215 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_N? "N" : "n"); |
216 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_Z? "Z" : "z"); |
217 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_V? "V" : "v"); |
218 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_C? "C" : "c"); |
219 |
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if (!bits32) { |
220 |
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debug(" xcc = "); |
221 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
222 |
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& SPARC_CCR_N? "N" : "n"); |
223 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
224 |
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& SPARC_CCR_Z? "Z" : "z"); |
225 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
226 |
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& SPARC_CCR_V? "V" : "v"); |
227 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
228 |
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& SPARC_CCR_C? "C" : "c"); |
229 |
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} |
230 |
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debug("\n"); |
231 |
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|
232 |
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if (bits32) |
233 |
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debug("cpu%i: psr = 0x%08"PRIx32"\n", |
234 |
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x, (uint32_t) cpu->cd.sparc.psr); |
235 |
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else |
236 |
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debug("cpu%i: pstate = 0x%016"PRIx64"\n", |
237 |
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x, (uint64_t) cpu->cd.sparc.pstate); |
238 |
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|
239 |
if (bits32) { |
if (bits32) { |
240 |
for (i=0; i<N_SPARC_REG; i++) { |
for (i=0; i<N_SPARC_REG; i++) { |
241 |
if ((i & 3) == 0) |
if ((i & 3) == 0) |
242 |
debug("cpu%i: ", x); |
debug("cpu%i: ", x); |
243 |
/* Skip the zero register: */ |
/* Skip the zero register: */ |
244 |
if (i==0) { |
if (i == SPARC_ZEROREG) { |
245 |
debug(" "); |
debug(" "); |
246 |
continue; |
continue; |
247 |
} |
} |
257 |
int r = ((i >> 1) & 15) | ((i&1) << 4); |
int r = ((i >> 1) & 15) | ((i&1) << 4); |
258 |
if ((i & 1) == 0) |
if ((i & 1) == 0) |
259 |
debug("cpu%i: ", x); |
debug("cpu%i: ", x); |
260 |
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|
261 |
/* Skip the zero register: */ |
/* Skip the zero register: */ |
262 |
if (r==0) { |
if (i == SPARC_ZEROREG) { |
263 |
debug(" "); |
debug(" "); |
264 |
continue; |
continue; |
265 |
} |
} |
266 |
|
|
267 |
debug("%s = ", sparc_regnames[r]); |
debug("%s = ", sparc_regnames[r]); |
268 |
debug("0x%016llx", (long long) |
debug("0x%016"PRIx64, (uint64_t) |
269 |
cpu->cd.sparc.r[r]); |
cpu->cd.sparc.r[r]); |
270 |
|
|
271 |
if ((i & 1) < 1) |
if ((i & 1) < 1) |
272 |
debug(" "); |
debug(" "); |
273 |
else |
else |
284 |
void sparc_cpu_register_match(struct machine *m, char *name, |
void sparc_cpu_register_match(struct machine *m, char *name, |
285 |
int writeflag, uint64_t *valuep, int *match_register) |
int writeflag, uint64_t *valuep, int *match_register) |
286 |
{ |
{ |
287 |
int cpunr = 0; |
int i, cpunr = 0; |
288 |
|
|
289 |
/* CPU number: */ |
/* CPU number: */ |
|
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|
290 |
/* TODO */ |
/* TODO */ |
291 |
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|
292 |
/* Register name: */ |
for (i=0; i<N_SPARC_REG; i++) { |
293 |
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if (strcasecmp(name, sparc_regnames[i]) == 0) { |
294 |
|
if (writeflag && i != SPARC_ZEROREG) |
295 |
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m->cpus[cpunr]->cd.sparc.r[i] = *valuep; |
296 |
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else |
297 |
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*valuep = m->cpus[cpunr]->cd.sparc.r[i]; |
298 |
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*match_register = 1; |
299 |
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} |
300 |
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} |
301 |
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|
302 |
if (strcasecmp(name, "pc") == 0) { |
if (strcasecmp(name, "pc") == 0) { |
303 |
if (writeflag) { |
if (writeflag) { |
304 |
m->cpus[cpunr]->pc = *valuep; |
m->cpus[cpunr]->pc = *valuep; |
305 |
} else |
} else { |
306 |
*valuep = m->cpus[cpunr]->pc; |
*valuep = m->cpus[cpunr]->pc; |
307 |
|
} |
308 |
*match_register = 1; |
*match_register = 1; |
309 |
} |
} |
310 |
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|
311 |
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if (strcasecmp(name, "y") == 0) { |
312 |
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if (writeflag) { |
313 |
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m->cpus[cpunr]->cd.sparc.y = (uint32_t) *valuep; |
314 |
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} else { |
315 |
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*valuep = (uint32_t) m->cpus[cpunr]->cd.sparc.y; |
316 |
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} |
317 |
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*match_register = 1; |
318 |
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} |
319 |
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|
320 |
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if (*match_register && m->cpus[cpunr]->is_32bit) |
321 |
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(*valuep) &= 0xffffffffULL; |
322 |
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} |
323 |
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|
324 |
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|
325 |
|
/* |
326 |
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* sparc_cpu_tlbdump(): |
327 |
|
* |
328 |
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* Called from the debugger to dump the TLB in a readable format. |
329 |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
330 |
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* |
331 |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
332 |
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* just dumped. |
333 |
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*/ |
334 |
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void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
335 |
|
{ |
336 |
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} |
337 |
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338 |
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|
339 |
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static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
340 |
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size_t maxlen, int len) |
341 |
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{ |
342 |
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char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
343 |
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if (len == 4) |
344 |
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value &= 0xffffffffULL; |
345 |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
346 |
|
if (len == 4) { |
347 |
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value = ((value & 0xff) << 24) + |
348 |
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((value & 0xff00) << 8) + |
349 |
|
((value & 0xff0000) >> 8) + |
350 |
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((value & 0xff000000) >> 24); |
351 |
|
} else { |
352 |
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value = ((value & 0xff) << 56) + |
353 |
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((value & 0xff00) << 40) + |
354 |
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((value & 0xff0000) << 24) + |
355 |
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((value & 0xff000000ULL) << 8) + |
356 |
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((value & 0xff00000000ULL) >> 8) + |
357 |
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((value & 0xff0000000000ULL) >> 24) + |
358 |
|
((value & 0xff000000000000ULL) >> 40) + |
359 |
|
((value & 0xff00000000000000ULL) >> 56); |
360 |
|
} |
361 |
|
} |
362 |
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snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
363 |
|
} |
364 |
|
|
365 |
|
|
366 |
|
/* |
367 |
|
* sparc_cpu_gdb_stub(): |
368 |
|
* |
369 |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
370 |
|
* on success, NULL on failure. |
371 |
|
*/ |
372 |
|
char *sparc_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
373 |
|
{ |
374 |
|
if (strcmp(cmd, "g") == 0) { |
375 |
|
int i; |
376 |
|
char *r; |
377 |
|
size_t wlen = cpu->is_32bit? |
378 |
|
sizeof(uint32_t) : sizeof(uint64_t); |
379 |
|
size_t len = 1 + 76 * wlen; |
380 |
|
r = malloc(len); |
381 |
|
if (r == NULL) { |
382 |
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fprintf(stderr, "out of memory\n"); |
383 |
|
exit(1); |
384 |
|
} |
385 |
|
r[0] = '\0'; |
386 |
|
/* TODO */ |
387 |
|
for (i=0; i<128; i++) |
388 |
|
add_response_word(cpu, r, i, len, wlen); |
389 |
|
return r; |
390 |
|
} |
391 |
|
|
392 |
|
if (cmd[0] == 'p') { |
393 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
394 |
|
size_t wlen = sizeof(uint32_t); |
395 |
|
/* TODO: cpu->is_32bit? sizeof(uint32_t) : sizeof(uint64_t); */ |
396 |
|
size_t len = 2 * wlen + 1; |
397 |
|
char *r = malloc(len); |
398 |
|
r[0] = '\0'; |
399 |
|
if (regnr >= 0 && regnr < N_SPARC_REG) { |
400 |
|
add_response_word(cpu, r, |
401 |
|
cpu->cd.sparc.r[regnr], len, wlen); |
402 |
|
} else if (regnr == 0x44) { |
403 |
|
add_response_word(cpu, r, cpu->pc, len, wlen); |
404 |
|
/* TODO: |
405 |
|
20..3f = f0..f31 |
406 |
|
40 = y |
407 |
|
41 = psr |
408 |
|
42 = wim |
409 |
|
43 = tbr |
410 |
|
45 = npc |
411 |
|
46 = fsr |
412 |
|
47 = csr |
413 |
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*/ |
414 |
|
} else { |
415 |
|
/* Unimplemented: */ |
416 |
|
add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
417 |
|
} |
418 |
|
return r; |
419 |
|
} |
420 |
|
|
421 |
|
fatal("sparc_cpu_gdb_stub(): TODO\n"); |
422 |
|
return NULL; |
423 |
} |
} |
424 |
|
|
425 |
|
|
444 |
|
|
445 |
|
|
446 |
/* |
/* |
447 |
|
* sparc_cpu_instruction_has_delayslot(): |
448 |
|
* |
449 |
|
* Return 1 if an opcode is a branch, 0 otherwise. |
450 |
|
*/ |
451 |
|
int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib) |
452 |
|
{ |
453 |
|
uint32_t iword = *((uint32_t *)&ib[0]); |
454 |
|
int hi2, op2; |
455 |
|
|
456 |
|
iword = BE32_TO_HOST(iword); |
457 |
|
|
458 |
|
hi2 = iword >> 30; |
459 |
|
op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f); |
460 |
|
|
461 |
|
switch (hi2) { |
462 |
|
case 0: /* conditional branch */ |
463 |
|
switch (op2) { |
464 |
|
case 1: |
465 |
|
case 2: |
466 |
|
case 3: return 1; |
467 |
|
} |
468 |
|
break; |
469 |
|
case 1: /* call */ |
470 |
|
return 1; |
471 |
|
case 2: /* misc alu instructions */ |
472 |
|
switch (op2) { |
473 |
|
case 56:/* jump and link */ |
474 |
|
return 1; |
475 |
|
} |
476 |
|
break; |
477 |
|
} |
478 |
|
|
479 |
|
return 0; |
480 |
|
} |
481 |
|
|
482 |
|
|
483 |
|
/* |
484 |
* sparc_cpu_disassemble_instr(): |
* sparc_cpu_disassemble_instr(): |
485 |
* |
* |
486 |
* Convert an instruction word into human readable format, for instruction |
* Convert an instruction word into human readable format, for instruction |
493 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
494 |
*/ |
*/ |
495 |
int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
496 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
497 |
{ |
{ |
498 |
uint64_t offset, tmp; |
uint64_t offset, tmp; |
499 |
uint32_t iword; |
uint32_t iword; |
500 |
int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0; |
int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0; |
501 |
int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p; |
int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p; |
502 |
char *symbol, *mnem; |
char *symbol, *mnem, *rd_name, *rs_name; |
503 |
|
|
504 |
if (running) |
if (running) |
505 |
dumpaddr = cpu->pc; |
dumpaddr = cpu->pc; |
513 |
debug("cpu%i: ", cpu->cpu_id); |
debug("cpu%i: ", cpu->cpu_id); |
514 |
|
|
515 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
516 |
debug("%08x", (int)dumpaddr); |
debug("%08"PRIx32, (uint32_t) dumpaddr); |
517 |
else |
else |
518 |
debug("%016llx", (long long)dumpaddr); |
debug("%016"PRIx64, (uint64_t) dumpaddr); |
519 |
|
|
520 |
iword = *(uint32_t *)&instr[0]; |
iword = *(uint32_t *)&instr[0]; |
521 |
iword = BE32_TO_HOST(iword); |
iword = BE32_TO_HOST(iword); |
522 |
|
|
523 |
debug(": %08x\t", iword); |
debug(": %08x", iword); |
524 |
|
|
525 |
|
if (running && cpu->delay_slot) |
526 |
|
debug(" (d)"); |
527 |
|
|
528 |
|
debug("\t"); |
529 |
|
|
530 |
|
|
531 |
/* |
/* |
532 |
* Decode the instruction: |
* Decode the instruction: |
587 |
} |
} |
588 |
tmp = (int64_t)(int32_t)tmps; |
tmp = (int64_t)(int32_t)tmps; |
589 |
tmp += dumpaddr; |
tmp += dumpaddr; |
590 |
debug("0x%llx", (long long)tmp); |
debug("0x%"PRIx64, (uint64_t) tmp); |
591 |
symbol = get_symbol_name(&cpu->machine-> |
symbol = get_symbol_name(&cpu->machine-> |
592 |
symbol_context, tmp, &offset); |
symbol_context, tmp, &offset); |
593 |
if (symbol != NULL) |
if (symbol != NULL) |
608 |
|
|
609 |
case 1: tmp = (int32_t)iword << 2; |
case 1: tmp = (int32_t)iword << 2; |
610 |
tmp += dumpaddr; |
tmp += dumpaddr; |
611 |
debug("call\t0x%llx", (long long)tmp); |
debug("call\t0x%"PRIx64, (uint64_t) tmp); |
612 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
613 |
tmp, &offset); |
tmp, &offset); |
614 |
if (symbol != NULL) |
if (symbol != NULL) |
616 |
break; |
break; |
617 |
|
|
618 |
case 2: mnem = sparc_alu_names[op2]; |
case 2: mnem = sparc_alu_names[op2]; |
619 |
|
rs_name = sparc_regnames[rs1]; |
620 |
|
rd_name = sparc_regnames[rd]; |
621 |
switch (op2) { |
switch (op2) { |
622 |
case 0: /* add */ |
case 0: /* add */ |
623 |
if (rd == rs1 && (iword & 0x3fff) == 0x2001) { |
if (rd == rs1 && (iword & 0x3fff) == 0x2001) { |
652 |
} else |
} else |
653 |
siconst &= 0x1f; |
siconst &= 0x1f; |
654 |
break; |
break; |
655 |
|
case 40:/* rd on pre-sparcv9, membar etc on sparcv9 */ |
656 |
|
no_rs2 = 1; |
657 |
|
rs_name = "UNIMPLEMENTED"; |
658 |
|
switch (rs1) { |
659 |
|
case 0: rs_name = "y"; break; |
660 |
|
case 2: rs_name = "ccr"; break; |
661 |
|
case 3: rs_name = "asi"; break; |
662 |
|
case 4: rs_name = "tick"; break; |
663 |
|
case 5: rs_name = "pc"; break; |
664 |
|
case 6: rs_name = "fprs"; break; |
665 |
|
case 15:/* membar etc. */ |
666 |
|
if ((iword >> 13) & 1) { |
667 |
|
no_rd = 1; |
668 |
|
mnem = "membar"; |
669 |
|
rs_name = "#TODO"; |
670 |
|
} |
671 |
|
break; |
672 |
|
case 23:rs_name = "tick_cmpr"; break; /* v9 ? */ |
673 |
|
} |
674 |
|
break; |
675 |
|
case 41:rs_name = "psr"; |
676 |
|
no_rs2 = 1; |
677 |
|
break; |
678 |
|
case 42:rs_name = "wim"; |
679 |
|
no_rs2 = 1; |
680 |
|
break; |
681 |
case 43:/* ? */ |
case 43:/* ? */ |
682 |
|
/* TODO: pre-sparcv9: rd, rs_name = "tbr"; */ |
683 |
if (iword == 0x81580000) { |
if (iword == 0x81580000) { |
684 |
mnem = "flushw"; |
mnem = "flushw"; |
685 |
no_rs1 = no_rs2 = no_rd = 1; |
no_rs1 = no_rs2 = no_rd = 1; |
686 |
} |
} |
687 |
break; |
break; |
688 |
|
case 48:/* wr* (SPARCv8) */ |
689 |
|
mnem = "wr"; |
690 |
|
if (rs1 == SPARC_ZEROREG) |
691 |
|
no_rs1 = 1; |
692 |
|
switch (rd) { |
693 |
|
case 0: rd_name = "y"; break; |
694 |
|
case 2: rd_name = "ccr"; break; |
695 |
|
case 3: rd_name = "asi"; break; |
696 |
|
case 6: rd_name = "fprs"; break; |
697 |
|
case 23:rd_name = "tick_cmpr"; break; /* v9 ? */ |
698 |
|
default:rd_name = "UNIMPLEMENTED"; |
699 |
|
} |
700 |
|
break; |
701 |
case 49:/* ? */ |
case 49:/* ? */ |
702 |
if (iword == 0x83880000) { |
if (iword == 0x83880000) { |
703 |
mnem = "restored"; |
mnem = "restored"; |
704 |
no_rs1 = no_rs2 = no_rd = 1; |
no_rs1 = no_rs2 = no_rd = 1; |
705 |
} |
} |
706 |
break; |
break; |
707 |
|
case 50:/* wrpr */ |
708 |
|
rd_name = sparc_pregnames[rd]; |
709 |
|
if (rs1 == SPARC_ZEROREG) |
710 |
|
no_rs1 = 1; |
711 |
|
break; |
712 |
case 56:/* jmpl */ |
case 56:/* jmpl */ |
713 |
jmpl = 1; |
jmpl = 1; |
714 |
if (iword == 0x81c7e008) { |
if (iword == 0x81c7e008) { |
735 |
debug("x"); |
debug("x"); |
736 |
debug("\t"); |
debug("\t"); |
737 |
if (!no_rs1) |
if (!no_rs1) |
738 |
debug("%%%s", sparc_regnames[rs1]); |
debug("%%%s", rs_name); |
739 |
if (!no_rs1 && !no_rs2) { |
if (!no_rs1 && !no_rs2) { |
740 |
if (jmpl) |
if (jmpl) |
741 |
debug("+"); |
debug("+"); |
746 |
if ((iword >> 13) & 1) { |
if ((iword >> 13) & 1) { |
747 |
if (siconst >= -9 && siconst <= 9) |
if (siconst >= -9 && siconst <= 9) |
748 |
debug("%i", siconst); |
debug("%i", siconst); |
749 |
|
else if (siconst < 0 && (op2 == 0 || |
750 |
|
op2 == 4 || op2 == 20 || op2 == 60)) |
751 |
|
debug("-0x%x", -siconst); |
752 |
else |
else |
753 |
debug("0x%x", siconst); |
debug("0x%x", siconst); |
754 |
} else { |
} else { |
758 |
if ((!no_rs1 || !no_rs2) && !no_rd) |
if ((!no_rs1 || !no_rs2) && !no_rd) |
759 |
debug(","); |
debug(","); |
760 |
if (!no_rd) |
if (!no_rd) |
761 |
debug("%%%s", sparc_regnames[rd]); |
debug("%%%s", rd_name); |
762 |
break; |
break; |
763 |
|
|
764 |
case 3: debug("%s\t", sparc_loadstore_names[op2]); |
case 3: mnem = sparc_loadstore_names[op2]; |
765 |
|
switch (op2) { |
766 |
|
case 0: /* 'lduw' was called only 'ld' in pre-v9 */ |
767 |
|
if (cpu->cd.sparc.cpu_type.v < 9) |
768 |
|
mnem = "ld"; |
769 |
|
break; |
770 |
|
} |
771 |
|
debug("%s\t", mnem); |
772 |
if (op2 & 4) |
if (op2 & 4) |
773 |
debug("%%%s,", sparc_regnames[rd]); |
debug("%%%s,", sparc_regnames[rd]); |
774 |
debug("[%%%s", sparc_regnames[rs1]); |
debug("[%%%s", sparc_regnames[rs1]); |
782 |
debug("+%%%s", sparc_regnames[rs2]); |
debug("+%%%s", sparc_regnames[rs2]); |
783 |
} |
} |
784 |
debug("]"); |
debug("]"); |
785 |
if (asi != 0) |
if ((op2 & 0x30) == 0x10) |
786 |
debug("(%i)", asi); |
debug("(%i)", asi); |
787 |
if (!(op2 & 4)) |
if (!(op2 & 4)) |
788 |
debug(",%%%s", sparc_regnames[rd]); |
debug(",%%%s", sparc_regnames[rd]); |
794 |
} |
} |
795 |
|
|
796 |
|
|
797 |
|
/* |
798 |
|
* sparc_update_pstate(): |
799 |
|
* |
800 |
|
* Update the pstate register (64-bit sparcs). |
801 |
|
*/ |
802 |
|
static void sparc_update_pstate(struct cpu *cpu, uint64_t new_pstate) |
803 |
|
{ |
804 |
|
/* uint64_t old_pstate = cpu->cd.sparc.pstate; */ |
805 |
|
|
806 |
|
/* TODO: Check individual bits. */ |
807 |
|
|
808 |
|
cpu->cd.sparc.pstate = new_pstate; |
809 |
|
} |
810 |
|
|
811 |
|
|
812 |
#include "tmp_sparc_tail.c" |
#include "tmp_sparc_tail.c" |
813 |
|
|