1 |
/* |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_sparc.c,v 1.1 2005/08/29 14:36:41 debug Exp $ |
* $Id: cpu_sparc.c,v 1.42 2007/03/18 02:54:59 debug Exp $ |
29 |
* |
* |
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* SPARC CPU emulation. |
* SPARC CPU emulation. |
31 |
*/ |
*/ |
39 |
#include "machine.h" |
#include "machine.h" |
40 |
#include "memory.h" |
#include "memory.h" |
41 |
#include "misc.h" |
#include "misc.h" |
42 |
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#include "settings.h" |
43 |
#include "symbol.h" |
#include "symbol.h" |
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#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
47 |
/* #define DYNTRANS_32 */ |
#define DYNTRANS_DELAYSLOT |
48 |
#include "tmp_sparc_head.c" |
#include "tmp_sparc_head.c" |
49 |
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50 |
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51 |
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static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES; |
52 |
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static char *sparc_pregnames[N_SPARC_PREG] = SPARC_PREG_NAMES; |
53 |
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static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] = |
54 |
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SPARC_REGBRANCH_NAMES; |
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static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES; |
56 |
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static char *sparc_alu_names[N_ALU_INSTR_TYPES] = SPARC_ALU_NAMES; |
57 |
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static char *sparc_loadstore_names[N_LOADSTORE_TYPES] = SPARC_LOADSTORE_NAMES; |
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59 |
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60 |
/* |
/* |
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* sparc_cpu_new(): |
* sparc_cpu_new(): |
62 |
* |
* |
68 |
int sparc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, |
int sparc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, |
69 |
int cpu_id, char *cpu_type_name) |
int cpu_id, char *cpu_type_name) |
70 |
{ |
{ |
71 |
if (strcasecmp(cpu_type_name, "SPARCv9") != 0) |
int any_cache = 0; |
72 |
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int i = 0; |
73 |
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struct sparc_cpu_type_def cpu_type_defs[] = SPARC_CPU_TYPE_DEFS; |
74 |
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75 |
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/* Scan the cpu_type_defs list for this cpu type: */ |
76 |
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while (cpu_type_defs[i].name != NULL) { |
77 |
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if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) { |
78 |
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break; |
79 |
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} |
80 |
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i++; |
81 |
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} |
82 |
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if (cpu_type_defs[i].name == NULL) |
83 |
return 0; |
return 0; |
84 |
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|
85 |
cpu->memory_rw = sparc_memory_rw; |
cpu->memory_rw = sparc_memory_rw; |
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cpu->update_translation_table = sparc_update_translation_table; |
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cpu->invalidate_translation_caches_paddr = |
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sparc_invalidate_translation_caches_paddr; |
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cpu->invalidate_code_translation = |
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sparc_invalidate_code_translation; |
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86 |
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87 |
cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->cd.sparc.cpu_type = cpu_type_defs[i]; |
88 |
cpu->is_32bit = 0; |
cpu->name = cpu->cd.sparc.cpu_type.name; |
89 |
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cpu->byte_order = EMUL_BIG_ENDIAN; |
90 |
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cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0; |
91 |
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92 |
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cpu->instruction_has_delayslot = sparc_cpu_instruction_has_delayslot; |
93 |
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94 |
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/* TODO: Separate this into 64-bit vs 32-bit? */ |
95 |
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cpu->translate_v2p = sparc_translate_v2p; |
96 |
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|
97 |
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if (cpu->is_32bit) { |
98 |
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cpu->run_instr = sparc32_run_instr; |
99 |
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cpu->update_translation_table = |
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sparc32_update_translation_table; |
101 |
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cpu->invalidate_translation_caches = |
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sparc32_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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sparc32_invalidate_code_translation; |
105 |
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} else { |
106 |
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cpu->run_instr = sparc_run_instr; |
107 |
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cpu->update_translation_table = sparc_update_translation_table; |
108 |
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cpu->invalidate_translation_caches = |
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sparc_invalidate_translation_caches; |
110 |
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cpu->invalidate_code_translation = |
111 |
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sparc_invalidate_code_translation; |
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} |
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|
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
115 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
116 |
debug("%s", cpu->name); |
debug("%s", cpu->name); |
117 |
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|
118 |
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if (cpu->cd.sparc.cpu_type.icache_shift != 0) |
119 |
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any_cache = 1; |
120 |
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if (cpu->cd.sparc.cpu_type.dcache_shift != 0) |
121 |
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any_cache = 1; |
122 |
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if (cpu->cd.sparc.cpu_type.l2cache_shift != 0) |
123 |
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any_cache = 1; |
124 |
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125 |
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if (any_cache) { |
126 |
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debug(" (I+D = %i+%i KB", (int) |
127 |
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(1 << (cpu->cd.sparc.cpu_type.icache_shift-10)), |
128 |
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(int)(1<<(cpu->cd.sparc.cpu_type.dcache_shift-10))); |
129 |
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if (cpu->cd.sparc.cpu_type.l2cache_shift != 0) { |
130 |
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debug(", L2 = %i KB", |
131 |
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(int)(1 << (cpu->cd.sparc.cpu_type. |
132 |
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l2cache_shift-10))); |
133 |
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} |
134 |
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debug(")"); |
135 |
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} |
136 |
} |
} |
137 |
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138 |
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/* After a reset, the Tick register is not readable by user code: */ |
139 |
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cpu->cd.sparc.tick |= SPARC_TICK_NPT; |
140 |
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|
141 |
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/* Insert number of Windows and Trap levels into the version reg.: */ |
142 |
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cpu->cd.sparc.ver |= N_REG_WINDOWS | (MAXTL << SPARC_VER_MAXTL_SHIFT); |
143 |
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|
144 |
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/* Misc. initial settings suitable for userland emulation: */ |
145 |
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cpu->cd.sparc.cansave = cpu->cd.sparc.cpu_type.nwindows - 2; |
146 |
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cpu->cd.sparc.canrestore = 0; |
147 |
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cpu->cd.sparc.cleanwin = 1; |
148 |
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cpu->cd.sparc.otherwin = 0; |
149 |
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|
150 |
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if (cpu->cd.sparc.cansave + cpu->cd.sparc.canrestore |
151 |
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+ cpu->cd.sparc.otherwin != cpu->cd.sparc.cpu_type.nwindows - 2) { |
152 |
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fatal("Fatal internal error: inconsistent windowing " |
153 |
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"parameters!\n"); |
154 |
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exit(1); |
155 |
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} |
156 |
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|
157 |
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if (cpu->cd.sparc.cpu_type.nwindows > N_REG_WINDOWS) { |
158 |
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fatal("Fatal internal error: nwindows = %1 is more than %i\n", |
159 |
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cpu->cd.sparc.cpu_type.nwindows, N_REG_WINDOWS); |
160 |
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exit(1); |
161 |
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} |
162 |
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163 |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
164 |
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CPU_SETTINGS_ADD_REGISTER64("y", cpu->cd.sparc.y); |
165 |
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CPU_SETTINGS_ADD_REGISTER64("pstate", cpu->cd.sparc.pstate); |
166 |
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for (i=0; i<N_SPARC_REG; i++) |
167 |
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CPU_SETTINGS_ADD_REGISTER64(sparc_regnames[i], |
168 |
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cpu->cd.sparc.r[i]); |
169 |
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/* TODO: Handler for writes to the zero register! */ |
170 |
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|
171 |
return 1; |
return 1; |
172 |
} |
} |
173 |
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|
179 |
*/ |
*/ |
180 |
void sparc_cpu_list_available_types(void) |
void sparc_cpu_list_available_types(void) |
181 |
{ |
{ |
182 |
debug("SPARCv9\n"); |
int i, j; |
183 |
/* TODO */ |
struct sparc_cpu_type_def tdefs[] = SPARC_CPU_TYPE_DEFS; |
184 |
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|
185 |
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i = 0; |
186 |
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while (tdefs[i].name != NULL) { |
187 |
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debug("%s", tdefs[i].name); |
188 |
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for (j=16 - strlen(tdefs[i].name); j>0; j--) |
189 |
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debug(" "); |
190 |
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i++; |
191 |
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if ((i % 4) == 0 || tdefs[i].name == NULL) |
192 |
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debug("\n"); |
193 |
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} |
194 |
} |
} |
195 |
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196 |
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|
199 |
*/ |
*/ |
200 |
void sparc_cpu_dumpinfo(struct cpu *cpu) |
void sparc_cpu_dumpinfo(struct cpu *cpu) |
201 |
{ |
{ |
202 |
debug("\n"); |
debug(", %i-bit\n", cpu->cd.sparc.cpu_type.bits); |
|
/* TODO */ |
|
203 |
} |
} |
204 |
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205 |
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214 |
void sparc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
void sparc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
215 |
{ |
{ |
216 |
char *symbol; |
char *symbol; |
217 |
uint64_t offset, tmp; |
uint64_t offset; |
218 |
int i, x = cpu->cpu_id; |
int i, x = cpu->cpu_id; |
219 |
int bits32 = 0; |
int bits32 = cpu->is_32bit; |
220 |
|
|
221 |
if (gprs) { |
if (gprs) { |
222 |
/* Special registers (pc, ...) first: */ |
/* Special registers (pc, ...) first: */ |
223 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
224 |
cpu->pc, &offset); |
cpu->pc, &offset); |
225 |
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|
226 |
debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
227 |
if (bits32) |
if (bits32) |
228 |
debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t) cpu->pc); |
229 |
else |
else |
230 |
debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t) cpu->pc); |
231 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
232 |
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|
233 |
/* TODO */ |
debug("cpu%i: y = 0x%08"PRIx32" ", |
234 |
} |
x, (uint32_t)cpu->cd.sparc.y); |
235 |
} |
debug("icc = "); |
236 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_N? "N" : "n"); |
237 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_Z? "Z" : "z"); |
238 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_V? "V" : "v"); |
239 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_C? "C" : "c"); |
240 |
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if (!bits32) { |
241 |
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debug(" xcc = "); |
242 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
243 |
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& SPARC_CCR_N? "N" : "n"); |
244 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
245 |
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& SPARC_CCR_Z? "Z" : "z"); |
246 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
247 |
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& SPARC_CCR_V? "V" : "v"); |
248 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
249 |
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& SPARC_CCR_C? "C" : "c"); |
250 |
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} |
251 |
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debug("\n"); |
252 |
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|
253 |
/* |
if (bits32) |
254 |
* sparc_cpu_register_match(): |
debug("cpu%i: psr = 0x%08"PRIx32"\n", |
255 |
*/ |
x, (uint32_t) cpu->cd.sparc.psr); |
256 |
void sparc_cpu_register_match(struct machine *m, char *name, |
else |
257 |
int writeflag, uint64_t *valuep, int *match_register) |
debug("cpu%i: pstate = 0x%016"PRIx64"\n", |
258 |
{ |
x, (uint64_t) cpu->cd.sparc.pstate); |
|
int cpunr = 0; |
|
259 |
|
|
260 |
/* CPU number: */ |
if (bits32) { |
261 |
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for (i=0; i<N_SPARC_REG; i++) { |
262 |
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if ((i & 3) == 0) |
263 |
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debug("cpu%i: ", x); |
264 |
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/* Skip the zero register: */ |
265 |
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if (i == SPARC_ZEROREG) { |
266 |
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debug(" "); |
267 |
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continue; |
268 |
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} |
269 |
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debug("%s=", sparc_regnames[i]); |
270 |
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debug("0x%08x", (int) cpu->cd.sparc.r[i]); |
271 |
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if ((i & 3) < 3) |
272 |
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debug(" "); |
273 |
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else |
274 |
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debug("\n"); |
275 |
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} |
276 |
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} else { |
277 |
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for (i=0; i<N_SPARC_REG; i++) { |
278 |
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int r = ((i >> 1) & 15) | ((i&1) << 4); |
279 |
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if ((i & 1) == 0) |
280 |
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debug("cpu%i: ", x); |
281 |
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|
282 |
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/* Skip the zero register: */ |
283 |
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if (i == SPARC_ZEROREG) { |
284 |
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debug(" "); |
285 |
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continue; |
286 |
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} |
287 |
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|
288 |
|
debug("%s = ", sparc_regnames[r]); |
289 |
|
debug("0x%016"PRIx64, (uint64_t) |
290 |
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cpu->cd.sparc.r[r]); |
291 |
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|
292 |
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if ((i & 1) < 1) |
293 |
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debug(" "); |
294 |
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else |
295 |
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debug("\n"); |
296 |
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} |
297 |
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} |
298 |
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} |
299 |
|
|
300 |
/* TODO */ |
if (coprocs & 1) { |
301 |
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int sum; |
302 |
|
|
303 |
/* Register name: */ |
debug("cpu%i: cwp = 0x%02x\n", x, cpu->cd.sparc.cwp); |
304 |
if (strcasecmp(name, "pc") == 0) { |
debug("cpu%i: cansave = 0x%02x\n", x, cpu->cd.sparc.cansave); |
305 |
if (writeflag) { |
debug("cpu%i: canrestore = 0x%02x\n", x, |
306 |
m->cpus[cpunr]->pc = *valuep; |
cpu->cd.sparc.canrestore); |
307 |
} else |
debug("cpu%i: otherwin = 0x%02x\n", x, |
308 |
*valuep = m->cpus[cpunr]->pc; |
cpu->cd.sparc.otherwin); |
309 |
*match_register = 1; |
debug("cpu%i: cleanwin = 0x%02x\n", x, |
310 |
} |
cpu->cd.sparc.cleanwin); |
311 |
} |
|
312 |
|
sum = cpu->cd.sparc.cansave + cpu->cd.sparc.canrestore + |
313 |
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cpu->cd.sparc.otherwin; |
314 |
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debug("cpu%i: cansave + canrestore + otherwin = %i + %i + %i" |
315 |
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" = %i", x, cpu->cd.sparc.cansave, cpu->cd.sparc.canrestore, |
316 |
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cpu->cd.sparc.otherwin, sum); |
317 |
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if (sum == cpu->cd.sparc.cpu_type.nwindows - 2) |
318 |
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debug(" (consistent)\n"); |
319 |
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else |
320 |
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debug(" (INCONSISTENT!)\n"); |
321 |
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|
322 |
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debug("cpu%i: wstate: other = %i, normal = %i\n", |
323 |
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x, (cpu->cd.sparc.wstate & SPARC_WSTATE_OTHER_MASK) |
324 |
|
>> SPARC_WSTATE_OTHER_SHIFT, cpu->cd.sparc.wstate & |
325 |
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SPARC_WSTATE_NORMAL_MASK); |
326 |
|
|
327 |
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debug("cpu%i: asi = 0x%02x\n", x, cpu->cd.sparc.asi); |
328 |
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debug("cpu%i: tl = 0x%02x\n", x, cpu->cd.sparc.tl); |
329 |
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debug("cpu%i: pil = 0x%02x\n", x, cpu->cd.sparc.pil); |
330 |
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|
331 |
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for (i=0; i<MAXTL; i++) { |
332 |
|
debug("cpu%i: tpc[%i] = 0x", x, i); |
333 |
|
if (bits32) |
334 |
|
debug("%08"PRIx32"\n", |
335 |
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(uint32_t) cpu->cd.sparc.tpc[i]); |
336 |
|
else |
337 |
|
debug("%016"PRIx64"\n", |
338 |
|
(uint64_t) cpu->cd.sparc.tpc[i]); |
339 |
|
|
340 |
|
debug("cpu%i: tnpc[%i] = 0x", x, i); |
341 |
|
if (bits32) |
342 |
|
debug("%08"PRIx32"\n", |
343 |
|
(uint32_t) cpu->cd.sparc.tnpc[i]); |
344 |
|
else |
345 |
|
debug("%016"PRIx64"\n", |
346 |
|
(uint64_t) cpu->cd.sparc.tnpc[i]); |
347 |
|
|
348 |
|
debug("cpu%i: tstate[%i] = 0x", x, i); |
349 |
|
if (bits32) |
350 |
|
debug("%08"PRIx32"\n", |
351 |
|
(uint32_t) cpu->cd.sparc.tstate[i]); |
352 |
|
else |
353 |
|
debug("%016"PRIx64"\n", |
354 |
|
(uint64_t) cpu->cd.sparc.tstate[i]); |
355 |
|
|
356 |
|
debug("cpu%i: ttype[%i] = 0x"PRIx32"\n", |
357 |
|
x, i, cpu->cd.sparc.ttype[i]); |
358 |
|
} |
359 |
|
|
360 |
/* |
debug("cpu%i: tba = 0x", x); |
361 |
* sparc_cpu_show_full_statistics(): |
if (bits32) |
362 |
* |
debug("%08"PRIx32"\n", (uint32_t) cpu->cd.sparc.tba); |
363 |
* Show detailed statistics on opcode usage on each cpu. |
else |
364 |
*/ |
debug("%016"PRIx64"\n", (uint64_t) cpu->cd.sparc.tba); |
365 |
void sparc_cpu_show_full_statistics(struct machine *m) |
} |
|
{ |
|
|
fatal("sparc_cpu_show_full_statistics(): TODO\n"); |
|
366 |
} |
} |
367 |
|
|
368 |
|
|
377 |
*/ |
*/ |
378 |
void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
379 |
{ |
{ |
380 |
fatal("sparc_cpu_tlbdump(): TODO\n"); |
} |
381 |
|
|
382 |
|
|
383 |
|
static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
384 |
|
size_t maxlen, int len) |
385 |
|
{ |
386 |
|
char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
387 |
|
if (len == 4) |
388 |
|
value &= 0xffffffffULL; |
389 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
390 |
|
if (len == 4) { |
391 |
|
value = ((value & 0xff) << 24) + |
392 |
|
((value & 0xff00) << 8) + |
393 |
|
((value & 0xff0000) >> 8) + |
394 |
|
((value & 0xff000000) >> 24); |
395 |
|
} else { |
396 |
|
value = ((value & 0xff) << 56) + |
397 |
|
((value & 0xff00) << 40) + |
398 |
|
((value & 0xff0000) << 24) + |
399 |
|
((value & 0xff000000ULL) << 8) + |
400 |
|
((value & 0xff00000000ULL) >> 8) + |
401 |
|
((value & 0xff0000000000ULL) >> 24) + |
402 |
|
((value & 0xff000000000000ULL) >> 40) + |
403 |
|
((value & 0xff00000000000000ULL) >> 56); |
404 |
|
} |
405 |
|
} |
406 |
|
snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
407 |
|
} |
408 |
|
|
409 |
|
|
410 |
|
/* |
411 |
|
* sparc_cpu_gdb_stub(): |
412 |
|
* |
413 |
|
* Execute a "remote GDB" command. Returns a newly allocated response string |
414 |
|
* on success, NULL on failure. |
415 |
|
*/ |
416 |
|
char *sparc_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
417 |
|
{ |
418 |
|
if (strcmp(cmd, "g") == 0) { |
419 |
|
int i; |
420 |
|
char *r; |
421 |
|
size_t wlen = cpu->is_32bit? |
422 |
|
sizeof(uint32_t) : sizeof(uint64_t); |
423 |
|
size_t len = 1 + 76 * wlen; |
424 |
|
r = malloc(len); |
425 |
|
if (r == NULL) { |
426 |
|
fprintf(stderr, "out of memory\n"); |
427 |
|
exit(1); |
428 |
|
} |
429 |
|
r[0] = '\0'; |
430 |
|
/* TODO */ |
431 |
|
for (i=0; i<128; i++) |
432 |
|
add_response_word(cpu, r, i, len, wlen); |
433 |
|
return r; |
434 |
|
} |
435 |
|
|
436 |
|
if (cmd[0] == 'p') { |
437 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
438 |
|
size_t wlen = sizeof(uint32_t); |
439 |
|
/* TODO: cpu->is_32bit? sizeof(uint32_t) : sizeof(uint64_t); */ |
440 |
|
size_t len = 2 * wlen + 1; |
441 |
|
char *r = malloc(len); |
442 |
|
r[0] = '\0'; |
443 |
|
if (regnr >= 0 && regnr < N_SPARC_REG) { |
444 |
|
add_response_word(cpu, r, |
445 |
|
cpu->cd.sparc.r[regnr], len, wlen); |
446 |
|
} else if (regnr == 0x44) { |
447 |
|
add_response_word(cpu, r, cpu->pc, len, wlen); |
448 |
|
/* TODO: |
449 |
|
20..3f = f0..f31 |
450 |
|
40 = y |
451 |
|
41 = psr |
452 |
|
42 = wim |
453 |
|
43 = tbr |
454 |
|
45 = npc |
455 |
|
46 = fsr |
456 |
|
47 = csr |
457 |
|
*/ |
458 |
|
} else { |
459 |
|
/* Unimplemented: */ |
460 |
|
add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
461 |
|
} |
462 |
|
return r; |
463 |
|
} |
464 |
|
|
465 |
|
fatal("sparc_cpu_gdb_stub(): TODO\n"); |
466 |
|
return NULL; |
467 |
} |
} |
468 |
|
|
469 |
|
|
488 |
|
|
489 |
|
|
490 |
/* |
/* |
491 |
|
* sparc_cpu_instruction_has_delayslot(): |
492 |
|
* |
493 |
|
* Return 1 if an opcode is a branch, 0 otherwise. |
494 |
|
*/ |
495 |
|
int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib) |
496 |
|
{ |
497 |
|
uint32_t iword = *((uint32_t *)&ib[0]); |
498 |
|
int hi2, op2; |
499 |
|
|
500 |
|
iword = BE32_TO_HOST(iword); |
501 |
|
|
502 |
|
hi2 = iword >> 30; |
503 |
|
op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f); |
504 |
|
|
505 |
|
switch (hi2) { |
506 |
|
case 0: /* conditional branch */ |
507 |
|
switch (op2) { |
508 |
|
case 1: |
509 |
|
case 2: |
510 |
|
case 3: return 1; |
511 |
|
} |
512 |
|
break; |
513 |
|
case 1: /* call */ |
514 |
|
return 1; |
515 |
|
case 2: /* misc alu instructions */ |
516 |
|
switch (op2) { |
517 |
|
case 56:/* jump and link */ |
518 |
|
return 1; |
519 |
|
case 57:/* return */ |
520 |
|
return 1; |
521 |
|
} |
522 |
|
break; |
523 |
|
} |
524 |
|
|
525 |
|
return 0; |
526 |
|
} |
527 |
|
|
528 |
|
|
529 |
|
/* |
530 |
* sparc_cpu_disassemble_instr(): |
* sparc_cpu_disassemble_instr(): |
531 |
* |
* |
532 |
* Convert an instruction word into human readable format, for instruction |
* Convert an instruction word into human readable format, for instruction |
539 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
540 |
*/ |
*/ |
541 |
int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
542 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
543 |
{ |
{ |
544 |
uint64_t offset, addr; |
uint64_t offset, tmp; |
545 |
uint32_t iword; |
uint32_t iword; |
546 |
int hi6; |
int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0; |
547 |
char *symbol, *mnem = "ERROR"; |
int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p; |
548 |
|
char *symbol, *mnem, *rd_name, *rs_name; |
549 |
|
|
550 |
if (running) |
if (running) |
551 |
dumpaddr = cpu->pc; |
dumpaddr = cpu->pc; |
558 |
if (cpu->machine->ncpus > 1 && running) |
if (cpu->machine->ncpus > 1 && running) |
559 |
debug("cpu%i: ", cpu->cpu_id); |
debug("cpu%i: ", cpu->cpu_id); |
560 |
|
|
561 |
/* if (cpu->cd.sparc.bits == 32) |
if (cpu->is_32bit) |
562 |
debug("%08x", (int)dumpaddr); |
debug("%08"PRIx32, (uint32_t) dumpaddr); |
563 |
else |
else |
564 |
*/ debug("%016llx", (long long)dumpaddr); |
debug("%016"PRIx64, (uint64_t) dumpaddr); |
565 |
|
|
566 |
iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) |
iword = *(uint32_t *)&instr[0]; |
567 |
+ instr[3]; |
iword = BE32_TO_HOST(iword); |
568 |
|
|
569 |
|
debug(": %08x", iword); |
570 |
|
|
571 |
|
if (running && cpu->delay_slot) |
572 |
|
debug(" (d)"); |
573 |
|
|
574 |
|
debug("\t"); |
575 |
|
|
|
debug(": %08x\t", iword); |
|
576 |
|
|
577 |
/* |
/* |
578 |
* Decode the instruction: |
* Decode the instruction: |
579 |
|
* |
580 |
|
* http://www.cs.unm.edu/~maccabe/classes/341/labman/node9.html is a |
581 |
|
* good quick description of SPARC instruction encoding. |
582 |
*/ |
*/ |
583 |
|
|
584 |
hi6 = iword >> 26; |
hi2 = iword >> 30; |
585 |
|
rd = (iword >> 25) & 31; |
586 |
switch (hi6) { |
btype = rd & (N_SPARC_BRANCH_TYPES - 1); |
587 |
default: |
rs1 = (iword >> 14) & 31; |
588 |
/* TODO */ |
asi = (iword >> 5) & 0xff; |
589 |
debug("unimplemented hi6 = 0x%02x", hi6); |
rs2 = iword & 31; |
590 |
|
siconst = (int16_t)((iword & 0x1fff) << 3) >> 3; |
591 |
|
op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f); |
592 |
|
cc = (iword >> 20) & 3; |
593 |
|
p = (iword >> 19) & 1; |
594 |
|
|
595 |
|
switch (hi2) { |
596 |
|
|
597 |
|
case 0: switch (op2) { |
598 |
|
|
599 |
|
case 0: debug("illtrap\t0x%x", iword & 0x3fffff); |
600 |
|
break; |
601 |
|
|
602 |
|
case 1: |
603 |
|
case 2: |
604 |
|
case 3: if (op2 == 3) |
605 |
|
debug("%s", sparc_regbranch_names[btype & 7]); |
606 |
|
else |
607 |
|
debug("%s", sparc_branch_names[btype]); |
608 |
|
if (rd & 16) |
609 |
|
debug(",a"); |
610 |
|
tmps = iword; |
611 |
|
switch (op2) { |
612 |
|
case 1: tmps <<= 13; |
613 |
|
tmps >>= 11; |
614 |
|
if (!p) |
615 |
|
debug(",pn"); |
616 |
|
debug("\t%%%s,", cc==0 ? "icc" : |
617 |
|
(cc==2 ? "xcc" : "UNKNOWN")); |
618 |
|
break; |
619 |
|
case 2: tmps <<= 10; |
620 |
|
tmps >>= 8; |
621 |
|
debug("\t"); |
622 |
|
break; |
623 |
|
case 3: if (btype & 8) |
624 |
|
debug("(INVALID)"); |
625 |
|
if (!p) |
626 |
|
debug(",pn"); |
627 |
|
debug("\t%%%s,", sparc_regnames[rs1]); |
628 |
|
tmps = ((iword & 0x300000) >> 6) |
629 |
|
| (iword & 0x3fff); |
630 |
|
tmps <<= 16; |
631 |
|
tmps >>= 14; |
632 |
|
break; |
633 |
|
} |
634 |
|
tmp = (int64_t)(int32_t)tmps; |
635 |
|
tmp += dumpaddr; |
636 |
|
debug("0x%"PRIx64, (uint64_t) tmp); |
637 |
|
symbol = get_symbol_name(&cpu->machine-> |
638 |
|
symbol_context, tmp, &offset); |
639 |
|
if (symbol != NULL) |
640 |
|
debug(" \t<%s>", symbol); |
641 |
|
break; |
642 |
|
|
643 |
|
case 4: if (rd == 0) { |
644 |
|
debug("nop"); |
645 |
|
break; |
646 |
|
} |
647 |
|
debug("sethi\t%%hi(0x%x),", (iword & 0x3fffff) << 10); |
648 |
|
debug("%%%s", sparc_regnames[rd]); |
649 |
|
break; |
650 |
|
|
651 |
|
default:debug("UNIMPLEMENTED hi2=%i, op2=0x%x", hi2, op2); |
652 |
|
} |
653 |
|
break; |
654 |
|
|
655 |
|
case 1: tmp = (int32_t)iword << 2; |
656 |
|
tmp += dumpaddr; |
657 |
|
debug("call\t0x%"PRIx64, (uint64_t) tmp); |
658 |
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
659 |
|
tmp, &offset); |
660 |
|
if (symbol != NULL) |
661 |
|
debug(" \t<%s>", symbol); |
662 |
|
break; |
663 |
|
|
664 |
|
case 2: mnem = sparc_alu_names[op2]; |
665 |
|
rs_name = sparc_regnames[rs1]; |
666 |
|
rd_name = sparc_regnames[rd]; |
667 |
|
switch (op2) { |
668 |
|
case 0: /* add */ |
669 |
|
if (rd == rs1 && (iword & 0x3fff) == 0x2001) { |
670 |
|
mnem = "inc"; |
671 |
|
no_rs1 = no_rs2 = 1; |
672 |
|
} |
673 |
|
break; |
674 |
|
case 2: /* or */ |
675 |
|
if (rs1 == 0) { |
676 |
|
mnem = "mov"; |
677 |
|
no_rs1 = 1; |
678 |
|
} |
679 |
|
break; |
680 |
|
case 4: /* sub */ |
681 |
|
if (rd == rs1 && (iword & 0x3fff) == 0x2001) { |
682 |
|
mnem = "dec"; |
683 |
|
no_rs1 = no_rs2 = 1; |
684 |
|
} |
685 |
|
break; |
686 |
|
case 20:/* subcc */ |
687 |
|
if (rd == 0) { |
688 |
|
mnem = "cmp"; |
689 |
|
no_rd = 1; |
690 |
|
} |
691 |
|
break; |
692 |
|
case 37:/* sll */ |
693 |
|
case 38:/* srl */ |
694 |
|
case 39:/* sra */ |
695 |
|
if (siconst & 0x1000) { |
696 |
|
siconst &= 0x3f; |
697 |
|
shift_x = 1; |
698 |
|
} else |
699 |
|
siconst &= 0x1f; |
700 |
|
break; |
701 |
|
case 40:/* rd on pre-sparcv9, membar etc on sparcv9 */ |
702 |
|
no_rs2 = 1; |
703 |
|
rs_name = "UNIMPLEMENTED"; |
704 |
|
switch (rs1) { |
705 |
|
case 0: rs_name = "y"; break; |
706 |
|
case 2: rs_name = "ccr"; break; |
707 |
|
case 3: rs_name = "asi"; break; |
708 |
|
case 4: rs_name = "tick"; break; |
709 |
|
case 5: rs_name = "pc"; break; |
710 |
|
case 6: rs_name = "fprs"; break; |
711 |
|
case 15:/* membar etc. */ |
712 |
|
if ((iword >> 13) & 1) { |
713 |
|
no_rd = 1; |
714 |
|
mnem = "membar"; |
715 |
|
rs_name = "#TODO"; |
716 |
|
} |
717 |
|
break; |
718 |
|
case 23:rs_name = "tick_cmpr"; break; /* v9 ? */ |
719 |
|
} |
720 |
|
break; |
721 |
|
case 41:rs_name = "psr"; |
722 |
|
no_rs2 = 1; |
723 |
|
break; |
724 |
|
case 42:/* TODO: something with wim only, on sparc v8? */ |
725 |
|
rs_name = sparc_pregnames[rs1]; |
726 |
|
no_rs2 = 1; |
727 |
|
break; |
728 |
|
case 43:/* ? */ |
729 |
|
/* TODO: pre-sparcv9: rd, rs_name = "tbr"; */ |
730 |
|
if (iword == 0x81580000) { |
731 |
|
mnem = "flushw"; |
732 |
|
no_rs1 = no_rs2 = no_rd = 1; |
733 |
|
} |
734 |
|
break; |
735 |
|
case 48:/* wr* (SPARCv8) */ |
736 |
|
mnem = "wr"; |
737 |
|
if (rs1 == SPARC_ZEROREG) |
738 |
|
no_rs1 = 1; |
739 |
|
switch (rd) { |
740 |
|
case 0: rd_name = "y"; break; |
741 |
|
case 2: rd_name = "ccr"; break; |
742 |
|
case 3: rd_name = "asi"; break; |
743 |
|
case 6: rd_name = "fprs"; break; |
744 |
|
case 23:rd_name = "tick_cmpr"; break; /* v9 ? */ |
745 |
|
default:rd_name = "UNIMPLEMENTED"; |
746 |
|
} |
747 |
|
break; |
748 |
|
case 49:/* ? */ |
749 |
|
if (iword == 0x83880000) { |
750 |
|
mnem = "restored"; |
751 |
|
no_rs1 = no_rs2 = no_rd = 1; |
752 |
|
} |
753 |
|
break; |
754 |
|
case 50:/* wrpr */ |
755 |
|
rd_name = sparc_pregnames[rd]; |
756 |
|
if (rs1 == SPARC_ZEROREG) |
757 |
|
no_rs1 = 1; |
758 |
|
break; |
759 |
|
case 56:/* jmpl */ |
760 |
|
jmpl = 1; |
761 |
|
if (iword == 0x81c7e008) { |
762 |
|
mnem = "ret"; |
763 |
|
no_rs1 = no_rs2 = no_rd = 1; |
764 |
|
} |
765 |
|
if (iword == 0x81c3e008) { |
766 |
|
mnem = "retl"; |
767 |
|
no_rs1 = no_rs2 = no_rd = 1; |
768 |
|
} |
769 |
|
break; |
770 |
|
case 61:/* restore */ |
771 |
|
if (iword == 0x81e80000) |
772 |
|
no_rs1 = no_rs2 = no_rd = 1; |
773 |
|
break; |
774 |
|
case 62:if (iword == 0x83f00000) { |
775 |
|
mnem = "retry"; |
776 |
|
no_rs1 = no_rs2 = no_rd = 1; |
777 |
|
} |
778 |
|
break; |
779 |
|
} |
780 |
|
debug("%s", mnem); |
781 |
|
if (shift_x) |
782 |
|
debug("x"); |
783 |
|
debug("\t"); |
784 |
|
if (!no_rs1) |
785 |
|
debug("%%%s", rs_name); |
786 |
|
if (!no_rs1 && !no_rs2) { |
787 |
|
if (jmpl) |
788 |
|
debug("+"); |
789 |
|
else |
790 |
|
debug(","); |
791 |
|
} |
792 |
|
if (!no_rs2) { |
793 |
|
if ((iword >> 13) & 1) { |
794 |
|
if (siconst >= -9 && siconst <= 9) |
795 |
|
debug("%i", siconst); |
796 |
|
else if (siconst < 0 && (op2 == 0 || |
797 |
|
op2 == 4 || op2 == 20 || op2 == 60)) |
798 |
|
debug("-0x%x", -siconst); |
799 |
|
else |
800 |
|
debug("0x%x", siconst); |
801 |
|
} else { |
802 |
|
debug("%%%s", sparc_regnames[rs2]); |
803 |
|
} |
804 |
|
} |
805 |
|
if ((!no_rs1 || !no_rs2) && !no_rd) |
806 |
|
debug(","); |
807 |
|
if (!no_rd) |
808 |
|
debug("%%%s", rd_name); |
809 |
|
break; |
810 |
|
|
811 |
|
case 3: mnem = sparc_loadstore_names[op2]; |
812 |
|
switch (op2) { |
813 |
|
case 0: /* 'lduw' was called only 'ld' in pre-v9 */ |
814 |
|
if (cpu->cd.sparc.cpu_type.v < 9) |
815 |
|
mnem = "ld"; |
816 |
|
break; |
817 |
|
} |
818 |
|
debug("%s\t", mnem); |
819 |
|
if (op2 & 4) |
820 |
|
debug("%%%s,", sparc_regnames[rd]); |
821 |
|
debug("[%%%s", sparc_regnames[rs1]); |
822 |
|
if ((iword >> 13) & 1) { |
823 |
|
if (siconst > 0) |
824 |
|
debug("+"); |
825 |
|
if (siconst != 0) |
826 |
|
debug("%i", siconst); |
827 |
|
} else { |
828 |
|
if (rs2 != 0) |
829 |
|
debug("+%%%s", sparc_regnames[rs2]); |
830 |
|
} |
831 |
|
debug("]"); |
832 |
|
if ((op2 & 0x30) == 0x10) |
833 |
|
debug("(%i)", asi); |
834 |
|
if (!(op2 & 4)) |
835 |
|
debug(",%%%s", sparc_regnames[rd]); |
836 |
|
break; |
837 |
} |
} |
838 |
|
|
839 |
debug("\n"); |
debug("\n"); |
841 |
} |
} |
842 |
|
|
843 |
|
|
844 |
|
/* |
845 |
|
* sparc_update_pstate(): |
846 |
|
* |
847 |
|
* Update the pstate register (64-bit sparcs). |
848 |
|
*/ |
849 |
|
static void sparc_update_pstate(struct cpu *cpu, uint64_t new_pstate) |
850 |
|
{ |
851 |
|
/* uint64_t old_pstate = cpu->cd.sparc.pstate; */ |
852 |
|
|
853 |
|
/* TODO: Check individual bits. */ |
854 |
|
|
855 |
|
cpu->cd.sparc.pstate = new_pstate; |
856 |
|
} |
857 |
|
|
858 |
|
|
859 |
#include "tmp_sparc_tail.c" |
#include "tmp_sparc_tail.c" |
860 |
|
|