/[gxemul]/trunk/src/cpus/cpu_sparc.c
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Contents of /trunk/src/cpus/cpu_sparc.c

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 19103 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_sparc.c,v 1.30 2006/06/16 18:31:26 debug Exp $
29 *
30 * SPARC CPU emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "cpu.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42 #include "symbol.h"
43
44
45 #define DYNTRANS_DUALMODE_32
46 #define DYNTRANS_DELAYSLOT
47 #include "tmp_sparc_head.c"
48
49
50 static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES;
51 static char *sparc_pregnames[N_SPARC_PREG] = SPARC_PREG_NAMES;
52 static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] =
53 SPARC_REGBRANCH_NAMES;
54 static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES;
55 static char *sparc_alu_names[N_ALU_INSTR_TYPES] = SPARC_ALU_NAMES;
56 static char *sparc_loadstore_names[N_LOADSTORE_TYPES] = SPARC_LOADSTORE_NAMES;
57
58
59 /*
60 * sparc_cpu_new():
61 *
62 * Create a new SPARC cpu object.
63 *
64 * Returns 1 on success, 0 if there was no matching SPARC processor with
65 * this cpu_type_name.
66 */
67 int sparc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
68 int cpu_id, char *cpu_type_name)
69 {
70 int any_cache = 0;
71 int i = 0;
72 struct sparc_cpu_type_def cpu_type_defs[] = SPARC_CPU_TYPE_DEFS;
73
74 /* Scan the cpu_type_defs list for this cpu type: */
75 while (cpu_type_defs[i].name != NULL) {
76 if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
77 break;
78 }
79 i++;
80 }
81 if (cpu_type_defs[i].name == NULL)
82 return 0;
83
84 cpu->memory_rw = sparc_memory_rw;
85
86 cpu->cd.sparc.cpu_type = cpu_type_defs[i];
87 cpu->name = cpu->cd.sparc.cpu_type.name;
88 cpu->byte_order = EMUL_BIG_ENDIAN;
89 cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0;
90
91 cpu->instruction_has_delayslot = sparc_cpu_instruction_has_delayslot;
92
93 if (cpu->is_32bit) {
94 cpu->update_translation_table =
95 sparc32_update_translation_table;
96 cpu->invalidate_translation_caches =
97 sparc32_invalidate_translation_caches;
98 cpu->invalidate_code_translation =
99 sparc32_invalidate_code_translation;
100 } else {
101 cpu->update_translation_table = sparc_update_translation_table;
102 cpu->invalidate_translation_caches =
103 sparc_invalidate_translation_caches;
104 cpu->invalidate_code_translation =
105 sparc_invalidate_code_translation;
106 }
107
108 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
109 if (cpu_id == 0) {
110 debug("%s", cpu->name);
111
112 if (cpu->cd.sparc.cpu_type.icache_shift != 0)
113 any_cache = 1;
114 if (cpu->cd.sparc.cpu_type.dcache_shift != 0)
115 any_cache = 1;
116 if (cpu->cd.sparc.cpu_type.l2cache_shift != 0)
117 any_cache = 1;
118
119 if (any_cache) {
120 debug(" (I+D = %i+%i KB", (int)
121 (1 << (cpu->cd.sparc.cpu_type.icache_shift-10)),
122 (int)(1<<(cpu->cd.sparc.cpu_type.dcache_shift-10)));
123 if (cpu->cd.sparc.cpu_type.l2cache_shift != 0) {
124 debug(", L2 = %i KB",
125 (int)(1 << (cpu->cd.sparc.cpu_type.
126 l2cache_shift-10)));
127 }
128 debug(")");
129 }
130 }
131
132 /* After a reset, the Tick register is not readable by user code: */
133 cpu->cd.sparc.tick |= SPARC_TICK_NPT;
134
135 /* Insert number of Windows and Trap levels into the version reg.: */
136 cpu->cd.sparc.ver |= MAXWIN | (MAXTL << SPARC_VER_MAXTL_SHIFT);
137
138 sparc_init_64bit_dummy_tables(cpu);
139
140 return 1;
141 }
142
143
144 /*
145 * sparc_cpu_list_available_types():
146 *
147 * Print a list of available SPARC CPU types.
148 */
149 void sparc_cpu_list_available_types(void)
150 {
151 int i, j;
152 struct sparc_cpu_type_def tdefs[] = SPARC_CPU_TYPE_DEFS;
153
154 i = 0;
155 while (tdefs[i].name != NULL) {
156 debug("%s", tdefs[i].name);
157 for (j=16 - strlen(tdefs[i].name); j>0; j--)
158 debug(" ");
159 i++;
160 if ((i % 4) == 0 || tdefs[i].name == NULL)
161 debug("\n");
162 }
163 }
164
165
166 /*
167 * sparc_cpu_dumpinfo():
168 */
169 void sparc_cpu_dumpinfo(struct cpu *cpu)
170 {
171 debug(", %i-bit\n", cpu->cd.sparc.cpu_type.bits);
172 }
173
174
175 /*
176 * sparc_cpu_register_dump():
177 *
178 * Dump cpu registers in a relatively readable format.
179 *
180 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
181 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
182 */
183 void sparc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
184 {
185 char *symbol;
186 uint64_t offset;
187 int i, x = cpu->cpu_id;
188 int bits32 = cpu->is_32bit;
189
190 if (gprs) {
191 /* Special registers (pc, ...) first: */
192 symbol = get_symbol_name(&cpu->machine->symbol_context,
193 cpu->pc, &offset);
194
195 debug("cpu%i: pc = 0x", x);
196 if (bits32)
197 debug("%08"PRIx32, (uint32_t) cpu->pc);
198 else
199 debug("%016"PRIx64, (uint64_t) cpu->pc);
200 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
201
202 debug("cpu%i: y = 0x%08"PRIx32" ",
203 x, (uint32_t)cpu->cd.sparc.y);
204 debug("icc = ");
205 debug(cpu->cd.sparc.ccr & SPARC_CCR_N? "N" : "n");
206 debug(cpu->cd.sparc.ccr & SPARC_CCR_Z? "Z" : "z");
207 debug(cpu->cd.sparc.ccr & SPARC_CCR_V? "V" : "v");
208 debug(cpu->cd.sparc.ccr & SPARC_CCR_C? "C" : "c");
209 if (!bits32) {
210 debug(" xcc = ");
211 debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT)
212 & SPARC_CCR_N? "N" : "n");
213 debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT)
214 & SPARC_CCR_Z? "Z" : "z");
215 debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT)
216 & SPARC_CCR_V? "V" : "v");
217 debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT)
218 & SPARC_CCR_C? "C" : "c");
219 }
220 debug("\n");
221
222 if (bits32)
223 debug("cpu%i: psr = 0x%08"PRIx32"\n",
224 x, (uint32_t) cpu->cd.sparc.psr);
225 else
226 debug("cpu%i: pstate = 0x%016"PRIx64"\n",
227 x, (uint64_t) cpu->cd.sparc.pstate);
228
229 if (bits32) {
230 for (i=0; i<N_SPARC_REG; i++) {
231 if ((i & 3) == 0)
232 debug("cpu%i: ", x);
233 /* Skip the zero register: */
234 if (i == SPARC_ZEROREG) {
235 debug(" ");
236 continue;
237 }
238 debug("%s=", sparc_regnames[i]);
239 debug("0x%08x", (int) cpu->cd.sparc.r[i]);
240 if ((i & 3) < 3)
241 debug(" ");
242 else
243 debug("\n");
244 }
245 } else {
246 for (i=0; i<N_SPARC_REG; i++) {
247 int r = ((i >> 1) & 15) | ((i&1) << 4);
248 if ((i & 1) == 0)
249 debug("cpu%i: ", x);
250
251 /* Skip the zero register: */
252 if (i == SPARC_ZEROREG) {
253 debug(" ");
254 continue;
255 }
256
257 debug("%s = ", sparc_regnames[r]);
258 debug("0x%016"PRIx64, (uint64_t)
259 cpu->cd.sparc.r[r]);
260
261 if ((i & 1) < 1)
262 debug(" ");
263 else
264 debug("\n");
265 }
266 }
267 }
268 }
269
270
271 /*
272 * sparc_cpu_register_match():
273 */
274 void sparc_cpu_register_match(struct machine *m, char *name,
275 int writeflag, uint64_t *valuep, int *match_register)
276 {
277 int i, cpunr = 0;
278
279 /* CPU number: */
280 /* TODO */
281
282 for (i=0; i<N_SPARC_REG; i++) {
283 if (strcasecmp(name, sparc_regnames[i]) == 0) {
284 if (writeflag && i != SPARC_ZEROREG)
285 m->cpus[cpunr]->cd.sparc.r[i] = *valuep;
286 else
287 *valuep = m->cpus[cpunr]->cd.sparc.r[i];
288 *match_register = 1;
289 }
290 }
291
292 if (strcasecmp(name, "pc") == 0) {
293 if (writeflag) {
294 m->cpus[cpunr]->pc = *valuep;
295 } else {
296 *valuep = m->cpus[cpunr]->pc;
297 }
298 *match_register = 1;
299 }
300
301 if (strcasecmp(name, "y") == 0) {
302 if (writeflag) {
303 m->cpus[cpunr]->cd.sparc.y = (uint32_t) *valuep;
304 } else {
305 *valuep = (uint32_t) m->cpus[cpunr]->cd.sparc.y;
306 }
307 *match_register = 1;
308 }
309
310 if (*match_register && m->cpus[cpunr]->is_32bit)
311 (*valuep) &= 0xffffffffULL;
312 }
313
314
315 /*
316 * sparc_cpu_tlbdump():
317 *
318 * Called from the debugger to dump the TLB in a readable format.
319 * x is the cpu number to dump, or -1 to dump all CPUs.
320 *
321 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
322 * just dumped.
323 */
324 void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag)
325 {
326 }
327
328
329 static void add_response_word(struct cpu *cpu, char *r, uint64_t value,
330 size_t maxlen, int len)
331 {
332 char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64;
333 if (len == 4)
334 value &= 0xffffffffULL;
335 if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
336 if (len == 4) {
337 value = ((value & 0xff) << 24) +
338 ((value & 0xff00) << 8) +
339 ((value & 0xff0000) >> 8) +
340 ((value & 0xff000000) >> 24);
341 } else {
342 value = ((value & 0xff) << 56) +
343 ((value & 0xff00) << 40) +
344 ((value & 0xff0000) << 24) +
345 ((value & 0xff000000ULL) << 8) +
346 ((value & 0xff00000000ULL) >> 8) +
347 ((value & 0xff0000000000ULL) >> 24) +
348 ((value & 0xff000000000000ULL) >> 40) +
349 ((value & 0xff00000000000000ULL) >> 56);
350 }
351 }
352 snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value);
353 }
354
355
356 /*
357 * sparc_cpu_gdb_stub():
358 *
359 * Execute a "remote GDB" command. Returns a newly allocated response string
360 * on success, NULL on failure.
361 */
362 char *sparc_cpu_gdb_stub(struct cpu *cpu, char *cmd)
363 {
364 if (strcmp(cmd, "g") == 0) {
365 int i;
366 char *r;
367 size_t wlen = cpu->is_32bit?
368 sizeof(uint32_t) : sizeof(uint64_t);
369 size_t len = 1 + 76 * wlen;
370 r = malloc(len);
371 if (r == NULL) {
372 fprintf(stderr, "out of memory\n");
373 exit(1);
374 }
375 r[0] = '\0';
376 /* TODO */
377 for (i=0; i<128; i++)
378 add_response_word(cpu, r, i, len, wlen);
379 return r;
380 }
381
382 if (cmd[0] == 'p') {
383 int regnr = strtol(cmd + 1, NULL, 16);
384 size_t wlen = sizeof(uint32_t);
385 /* TODO: cpu->is_32bit? sizeof(uint32_t) : sizeof(uint64_t); */
386 size_t len = 2 * wlen + 1;
387 char *r = malloc(len);
388 r[0] = '\0';
389 if (regnr >= 0 && regnr < N_SPARC_REG) {
390 add_response_word(cpu, r,
391 cpu->cd.sparc.r[regnr], len, wlen);
392 } else if (regnr == 0x44) {
393 add_response_word(cpu, r, cpu->pc, len, wlen);
394 /* TODO:
395 20..3f = f0..f31
396 40 = y
397 41 = psr
398 42 = wim
399 43 = tbr
400 45 = npc
401 46 = fsr
402 47 = csr
403 */
404 } else {
405 /* Unimplemented: */
406 add_response_word(cpu, r, 0xcc000 + regnr, len, wlen);
407 }
408 return r;
409 }
410
411 fatal("sparc_cpu_gdb_stub(): TODO\n");
412 return NULL;
413 }
414
415
416 /*
417 * sparc_cpu_interrupt():
418 */
419 int sparc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
420 {
421 fatal("sparc_cpu_interrupt(): TODO\n");
422 return 0;
423 }
424
425
426 /*
427 * sparc_cpu_interrupt_ack():
428 */
429 int sparc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
430 {
431 /* fatal("sparc_cpu_interrupt_ack(): TODO\n"); */
432 return 0;
433 }
434
435
436 /*
437 * sparc_cpu_instruction_has_delayslot():
438 *
439 * Return 1 if an opcode is a branch, 0 otherwise.
440 */
441 int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
442 {
443 uint32_t iword = *((uint32_t *)&ib[0]);
444 int hi2, op2;
445
446 iword = BE32_TO_HOST(iword);
447
448 hi2 = iword >> 30;
449 op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f);
450
451 switch (hi2) {
452 case 0: /* conditional branch */
453 switch (op2) {
454 case 1:
455 case 2:
456 case 3: return 1;
457 }
458 break;
459 case 1: /* call */
460 return 1;
461 case 2: /* misc alu instructions */
462 switch (op2) {
463 case 56:/* jump and link */
464 return 1;
465 }
466 break;
467 }
468
469 return 0;
470 }
471
472
473 /*
474 * sparc_cpu_disassemble_instr():
475 *
476 * Convert an instruction word into human readable format, for instruction
477 * tracing.
478 *
479 * If running is 1, cpu->pc should be the address of the instruction.
480 *
481 * If running is 0, things that depend on the runtime environment (eg.
482 * register contents) will not be shown, and addr will be used instead of
483 * cpu->pc for relative addresses.
484 */
485 int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
486 int running, uint64_t dumpaddr)
487 {
488 uint64_t offset, tmp;
489 uint32_t iword;
490 int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0;
491 int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p;
492 char *symbol, *mnem, *rd_name, *rs_name;
493
494 if (running)
495 dumpaddr = cpu->pc;
496
497 symbol = get_symbol_name(&cpu->machine->symbol_context,
498 dumpaddr, &offset);
499 if (symbol != NULL && offset==0)
500 debug("<%s>\n", symbol);
501
502 if (cpu->machine->ncpus > 1 && running)
503 debug("cpu%i: ", cpu->cpu_id);
504
505 if (cpu->is_32bit)
506 debug("%08"PRIx32, (uint32_t) dumpaddr);
507 else
508 debug("%016"PRIx64, (uint64_t) dumpaddr);
509
510 iword = *(uint32_t *)&instr[0];
511 iword = BE32_TO_HOST(iword);
512
513 debug(": %08x", iword);
514
515 if (running && cpu->delay_slot)
516 debug(" (d)");
517
518 debug("\t");
519
520
521 /*
522 * Decode the instruction:
523 *
524 * http://www.cs.unm.edu/~maccabe/classes/341/labman/node9.html is a
525 * good quick description of SPARC instruction encoding.
526 */
527
528 hi2 = iword >> 30;
529 rd = (iword >> 25) & 31;
530 btype = rd & (N_SPARC_BRANCH_TYPES - 1);
531 rs1 = (iword >> 14) & 31;
532 asi = (iword >> 5) & 0xff;
533 rs2 = iword & 31;
534 siconst = (int16_t)((iword & 0x1fff) << 3) >> 3;
535 op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f);
536 cc = (iword >> 20) & 3;
537 p = (iword >> 19) & 1;
538
539 switch (hi2) {
540
541 case 0: switch (op2) {
542
543 case 0: debug("illtrap\t0x%x", iword & 0x3fffff);
544 break;
545
546 case 1:
547 case 2:
548 case 3: if (op2 == 3)
549 debug("%s", sparc_regbranch_names[btype & 7]);
550 else
551 debug("%s", sparc_branch_names[btype]);
552 if (rd & 16)
553 debug(",a");
554 tmps = iword;
555 switch (op2) {
556 case 1: tmps <<= 13;
557 tmps >>= 11;
558 if (!p)
559 debug(",pn");
560 debug("\t%%%s,", cc==0 ? "icc" :
561 (cc==2 ? "xcc" : "UNKNOWN"));
562 break;
563 case 2: tmps <<= 10;
564 tmps >>= 8;
565 debug("\t");
566 break;
567 case 3: if (btype & 8)
568 debug("(INVALID)");
569 if (!p)
570 debug(",pn");
571 debug("\t%%%s,", sparc_regnames[rs1]);
572 tmps = ((iword & 0x300000) >> 6)
573 | (iword & 0x3fff);
574 tmps <<= 16;
575 tmps >>= 14;
576 break;
577 }
578 tmp = (int64_t)(int32_t)tmps;
579 tmp += dumpaddr;
580 debug("0x%"PRIx64, (uint64_t) tmp);
581 symbol = get_symbol_name(&cpu->machine->
582 symbol_context, tmp, &offset);
583 if (symbol != NULL)
584 debug(" \t<%s>", symbol);
585 break;
586
587 case 4: if (rd == 0) {
588 debug("nop");
589 break;
590 }
591 debug("sethi\t%%hi(0x%x),", (iword & 0x3fffff) << 10);
592 debug("%%%s", sparc_regnames[rd]);
593 break;
594
595 default:debug("UNIMPLEMENTED hi2=%i, op2=0x%x", hi2, op2);
596 }
597 break;
598
599 case 1: tmp = (int32_t)iword << 2;
600 tmp += dumpaddr;
601 debug("call\t0x%"PRIx64, (uint64_t) tmp);
602 symbol = get_symbol_name(&cpu->machine->symbol_context,
603 tmp, &offset);
604 if (symbol != NULL)
605 debug(" \t<%s>", symbol);
606 break;
607
608 case 2: mnem = sparc_alu_names[op2];
609 rs_name = sparc_regnames[rs1];
610 rd_name = sparc_regnames[rd];
611 switch (op2) {
612 case 0: /* add */
613 if (rd == rs1 && (iword & 0x3fff) == 0x2001) {
614 mnem = "inc";
615 no_rs1 = no_rs2 = 1;
616 }
617 break;
618 case 2: /* or */
619 if (rs1 == 0) {
620 mnem = "mov";
621 no_rs1 = 1;
622 }
623 break;
624 case 4: /* sub */
625 if (rd == rs1 && (iword & 0x3fff) == 0x2001) {
626 mnem = "dec";
627 no_rs1 = no_rs2 = 1;
628 }
629 break;
630 case 20:/* subcc */
631 if (rd == 0) {
632 mnem = "cmp";
633 no_rd = 1;
634 }
635 break;
636 case 37:/* sll */
637 case 38:/* srl */
638 case 39:/* sra */
639 if (siconst & 0x1000) {
640 siconst &= 0x3f;
641 shift_x = 1;
642 } else
643 siconst &= 0x1f;
644 break;
645 case 40:/* rd on pre-sparcv9, membar etc on sparcv9 */
646 no_rs2 = 1;
647 rs_name = "UNIMPLEMENTED";
648 switch (rs1) {
649 case 0: rs_name = "y"; break;
650 case 2: rs_name = "ccr"; break;
651 case 3: rs_name = "asi"; break;
652 case 4: rs_name = "tick"; break;
653 case 5: rs_name = "pc"; break;
654 case 6: rs_name = "fprs"; break;
655 case 15:/* membar etc. */
656 if ((iword >> 13) & 1) {
657 no_rd = 1;
658 mnem = "membar";
659 rs_name = "#TODO";
660 }
661 break;
662 case 23:rs_name = "tick_cmpr"; break; /* v9 ? */
663 }
664 break;
665 case 41:rs_name = "psr";
666 no_rs2 = 1;
667 break;
668 case 42:rs_name = "wim";
669 no_rs2 = 1;
670 break;
671 case 43:/* ? */
672 /* TODO: pre-sparcv9: rd, rs_name = "tbr"; */
673 if (iword == 0x81580000) {
674 mnem = "flushw";
675 no_rs1 = no_rs2 = no_rd = 1;
676 }
677 break;
678 case 48:/* wr* (SPARCv8) */
679 mnem = "wr";
680 if (rs1 == SPARC_ZEROREG)
681 no_rs1 = 1;
682 switch (rd) {
683 case 0: rd_name = "y"; break;
684 case 2: rd_name = "ccr"; break;
685 case 3: rd_name = "asi"; break;
686 case 6: rd_name = "fprs"; break;
687 case 23:rd_name = "tick_cmpr"; break; /* v9 ? */
688 default:rd_name = "UNIMPLEMENTED";
689 }
690 break;
691 case 49:/* ? */
692 if (iword == 0x83880000) {
693 mnem = "restored";
694 no_rs1 = no_rs2 = no_rd = 1;
695 }
696 break;
697 case 50:/* wrpr */
698 rd_name = sparc_pregnames[rd];
699 if (rs1 == SPARC_ZEROREG)
700 no_rs1 = 1;
701 break;
702 case 56:/* jmpl */
703 jmpl = 1;
704 if (iword == 0x81c7e008) {
705 mnem = "ret";
706 no_rs1 = no_rs2 = no_rd = 1;
707 }
708 if (iword == 0x81c3e008) {
709 mnem = "retl";
710 no_rs1 = no_rs2 = no_rd = 1;
711 }
712 break;
713 case 61:/* restore */
714 if (iword == 0x81e80000)
715 no_rs1 = no_rs2 = no_rd = 1;
716 break;
717 case 62:if (iword == 0x83f00000) {
718 mnem = "retry";
719 no_rs1 = no_rs2 = no_rd = 1;
720 }
721 break;
722 }
723 debug("%s", mnem);
724 if (shift_x)
725 debug("x");
726 debug("\t");
727 if (!no_rs1)
728 debug("%%%s", rs_name);
729 if (!no_rs1 && !no_rs2) {
730 if (jmpl)
731 debug("+");
732 else
733 debug(",");
734 }
735 if (!no_rs2) {
736 if ((iword >> 13) & 1) {
737 if (siconst >= -9 && siconst <= 9)
738 debug("%i", siconst);
739 else
740 debug("0x%x", siconst);
741 } else {
742 debug("%%%s", sparc_regnames[rs2]);
743 }
744 }
745 if ((!no_rs1 || !no_rs2) && !no_rd)
746 debug(",");
747 if (!no_rd)
748 debug("%%%s", rd_name);
749 break;
750
751 case 3: debug("%s\t", sparc_loadstore_names[op2]);
752 if (op2 & 4)
753 debug("%%%s,", sparc_regnames[rd]);
754 debug("[%%%s", sparc_regnames[rs1]);
755 if ((iword >> 13) & 1) {
756 if (siconst > 0)
757 debug("+");
758 if (siconst != 0)
759 debug("%i", siconst);
760 } else {
761 if (rs2 != 0)
762 debug("+%%%s", sparc_regnames[rs2]);
763 }
764 debug("]");
765 if (asi != 0)
766 debug("(%i)", asi);
767 if (!(op2 & 4))
768 debug(",%%%s", sparc_regnames[rd]);
769 break;
770 }
771
772 debug("\n");
773 return sizeof(iword);
774 }
775
776
777 /*
778 * sparc_update_pstate():
779 *
780 * Update the pstate register (64-bit sparcs).
781 */
782 static void sparc_update_pstate(struct cpu *cpu, uint64_t new_pstate)
783 {
784 /* uint64_t old_pstate = cpu->cd.sparc.pstate; */
785
786 /* TODO: Check individual bits. */
787
788 cpu->cd.sparc.pstate = new_pstate;
789 }
790
791
792 #include "tmp_sparc_tail.c"
793

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